参数资料
型号: NS7520B-1-C55
厂商: Digi International
文件页数: 27/68页
文件大小: 0K
描述: IC ARM MICROPROCESSOR 177BGA
标准包装: 160
系列: NET+ARM®
应用: 网络处理器
核心处理器: ARM7
程序存储器类型: 外部程序存储器
RAM 容量: 外部
接口: EBI/EMI,以太网,DMA,SPI,UART
输入/输出数: 16
电源电压: 1.4 V ~ 3.6 V
工作温度: -40°C ~ 85°C
安装类型: 表面贴装
封装/外壳: 177-LFBGA
包装: 托盘
供应商设备封装: 177-BGA(13x13)
Reset_timing
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29
Reset_timing
From a cold start, RESET_ must be asserted until all power supplies are above their specified
thresholds. An additional 8 microseconds is required for oscillator settling time (allow 40ms for
crystal startup).
Due to an internal three flip-flop delay on the external RESET_ signal, after the oscillator is
settled, RESET_ must be asserted for three periods of the XTALA1 clock in these situations:
Before release of reset after application of power
While valid power is maintained to initiate hot reset (reset while power is at or above
specified thresholds)
Before loss of valid power during power outage/power down
The PORTC4 output indicates the reset state of the chip. PORTC4 persists beyond the negation of
RESET_ for approximately 512 system clock cycles if the PLL is disabled. When the PLL is enabled,
PORTC4 persists beyond the negation of RESET_ to allow for PLL lock for 100 microseconds times
the ratio of the VCO to XTALA.
Reset timing parameters
Num
Description
Min
Typ
Max
Units
1
Power valid before reset negated
40
ms
Note: RESET_ should remain low
for at least 40ms after power
reaches 3.0V.
2
Reset asserted after power valid
3
TXTALA1
3
Reset asserted while power valid
3
TXTALA1
4
Reset asserted before power invalid
3
TXTALA1
4
3
2
1
VDD, VCC
XTALA1
RESET_
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