参数资料
型号: NSVD4001DR2G
厂商: ON Semiconductor
文件页数: 7/8页
文件大小: 0K
描述: IC LED DRIVER LINEAR 8-SOIC
标准包装: 2,500
系列: *
NUD4001, NSVD4001
THERMAL INFORMATION
PD + Jmax
NUD4001, NSVD4001 Power Dissipation
The power dissipation of the SO ? 8 is a function of the pad
size. This can vary from the minimum pad size for soldering
to a pad size given for maximum power dissipation. Power
dissipation for a surface mount device is determined by
T J(max) , the maximum rated junction temperature of the die,
R q JA , the thermal resistance from the device junction to
ambient, and the operating temperature, T A . Using the
values provided on the data sheet for the SO ? 8 package, P D
can be calculated as follows:
T * TA
R q JA
The values for the equation are found in the maximum
ratings table on the data sheet. Substituting these values into
the equation for an ambient temperature T A of 25 ° C, one can
calculate the power dissipation of the device which in this
case is 1.13 W.
reduce the thermal resistance. Figure 11 shows how the
thermal resistance changes for different copper areas.
Another alternative would be to use a ceramic substrate or
an aluminum core board such as Thermal Clad ? . Using a
board material such as Thermal Clad or an aluminum core
board, the power dissipation can be even doubled using the
same footprint.
180
160
140
120
100
PD + 150 ° C * 25 ° C + 1.13 W
110 ° C
The 110 ° C/W for the SO ? 8 package assumes the use of a
FR ? 4 copper board with an area of 2 square inches with 2 oz
80
60
0
1
2
3
4
5
6
7
8
9
10
coverage to achieve a power dissipation of 1.13 W. There are
other alternatives to achieving higher dissipation from the
SOIC package. One of them is to increase the copper area to
BOARD AREA (in 2 )
Figure 11. q JA versus Board Area
250
1S ? 36.9 sq. mm ? 0.057 in sq.
200
150
100
50
1S ? 75.8 sq. mm ? 0.117 in sq.
1S ? 150.0 sq. mm ? 0.233 in sq.
1S ? 321.5 sq. mm ? 0.498 in sq.
1S ? 681.0 sq. mm ? 1.056 in sq.
1S ? 1255.0 sq. mm ? 1.945 in sq.
0
0.000001
0.00001
0.0001
0.001
0.01
0.1
1
10
100
1000
TIME (sec)
Figure 12. Transient Thermal Response
http://onsemi.com
7
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