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参数资料
| 型号： | NT3980 |
| 厂商： | Electronic Theatre Controls, Inc. |
| 英文描述： | TFT LCD Source Driver |
| 中文描述： | TFT液晶显示器源驱动器 |
| 文件页数： | 10/13页 |
| 文件大小： | 119K |
| 代理商： | NT3980 |
NT3980
TFT LCD Source Driver
Version 1.0
10
October 16, 2001
Absolute Maximum Ratings*
Supply voltage, Vcc
-0.3V to 5V
Supply voltage, AV
DD
-0.3V to +12V
Input voltage, V1~ V10
-0.3 to AVDD+0.3
Input range(digital inputs)
-0.3 to Vcc+0.3
Storage temperature
-55
to 110
Operating temperature
to 75
DC Electrical Characteristics
(V
cc
=3.3V , AV
DD
=10V, AVSS=GND=0V, T
A
= -30
(For the digital circuit)
Parameter
Symbol
Min.
Typ.
Supply Voltage
Vcc
2.5
--
Low Level Input Voltage
Vil
0
-
High Level Input Voltage
Vih
0.7xVcc
-
High Level Output Voltage
Voh
0.7xVcc
-
Low Level Output Voltage
Vol
--
-
Input Leakage Current
Ii
-1
-
Gamma correction Current
Iref
--
800
Digital Operating Current
Icc
-
3
*Comments
-30
Stresses above those listed under "Absolute Maximum
Ratings" may
cause permanent damage to the device.
These are stress ratings only. Functional operation of this
device at these or under any other conditions above those
indicated in the operational sections of this specification are
not implied and exposure to absolute maximum rating
conditions for extended periods may affect device reliability.
~ 75
)
Max.
3.6
0.3xVcc
Vcc
--
0.3Vcc
1
1000
6
Unit
V
V
V
V
V
μ
A
For LD,CLK,SHL,Dxx,POL,REV1/2,DIO1/2
μ
A
For V1-V5=4.75V or V6-V10=4.75V
mA
Vcc=3.6V, AVDD=9.5V,fld=50kHz,fclk=45MHz
No load
Conditions
Digital power
For the digital circuit
For the digital circuit
DIO1(O), DIO2(O), Ioh=-0.4mA
DIO1(O), DIO2(O), Iol=0.4mA
(For the analog circuit)
Parameter
Supply Voltage
Input level of V1 ~ V5
Input level of V6 ~ V10
Output Voltage Deviation
Symbol
AVDD
Vref
Vref
Vvd
Min.
7.0
AVDD/2
0.1
--
--
--
Typ.
--
-
Max.
10
AVDD-0.1
AVDD/2
±
12
±
5
±
10
Unit
V
V
V
mV
mV
mV
Conditions
For the analog circuit power
Gamma correction voltage
Gamma correction voltage
Input data ‘ without’ offset cancellation
Input data ‘ with’ offset cancellation (Note1)
OUT1 ~ OUT384,input data 00 to FF.
±
6
±
2
±
5
Average output voltage
dispersion
Dynamic Range of Output
Low-Level Output Current
High-Level Output Current
Analog Operating Current
Vod
Vdr
IOL
IOH
IDD
0.1
-150
150
-
-
AVDD-0.1
-
-
12
V
μ
A
μ
A
mA
OUT1 ~ OUT384
OUT1 ~ OUT384; Vo=0.1V V.S 1.0V
OUT1 ~ OUT384; Vo=9.9V V.S 9V
Vcc=3.6V,AVDD=9.5V,fld=50kHz,fclk=45MHz
No load
For Input pins ,except DIO1,DIO2
For DIO1,DIO2
-300
300
6
Input capacitance1
Input capacitance2
C1
C2
--
--
5
10
10
15
pF
pF
(Note1) This chip needs 253 CLK cycles to use its 'offset cancellation' function to get a precision output voltage.
Please refer to the timing chart below :
CLK
Outputs
LD
1
2
252
5
4
3
253
254
Finish 'offset
cancellation'
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