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参数资料
| 型号： | NT5DS32M8AT |
| 厂商： | Electronic Theatre Controls, Inc. |
| 英文描述： | 256Mb DDR333/300 SDRAM |
| 中文描述： | 256Mb的DDR333/300内存 |
| 文件页数： | 14/27页 |
| 文件大小： | 269K |
| 代理商： | NT5DS32M8AT |
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NT5DS64M4AT NT5DS64M4AW
NT5DS32M8AT NT5DS32M8AW
256Mb DDR333/300 SDRAM
Preliminary
10/01
14
NANYA TECHNOLOGY CORP
. All rights reserved.
NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.
Truth Table 4: Current State Bank n - Command to Bank m (Different bank)
(Part 1 of 2)
Current State
CS
RAS
CAS
WE
Command
Action
Notes
Any
H
X
X
X
Deselect
NOP/continue previous operation
1-6
L
H
H
H
No Operation
NOP/continue previous operation
1-6
Idle
X
X
X
X
Any Command Otherwise
Allowed to Bank m
1-6
Row Activating,
Active, or
Precharging
L
L
H
H
Active
Select and activate row
1-6
L
H
L
H
Read
Select column and start Read burst
1-7
L
H
L
L
Write
Select column and start Write burst
1-7
L
L
H
L
Precharge
1-6
Read
(Auto Precharge
Disabled)
L
L
H
H
Active
Select and activate row
1-6
L
H
L
H
Read
Select column and start new Read burst
1-7
L
L
H
L
Precharge
1-6
Write
(Auto Precharge
Disabled)
L
L
H
H
Active
Select and activate row
1-6
L
H
L
H
Read
Select column and start Read burst
1-8
L
H
L
L
Write
Select column and start new Write burst
1-7
L
L
H
L
Precharge
1-6
1. This table applies when CKE n-1 was high and CKE n is high (see Truth Table 2: Clock Enable (CKE) and after t
XSNR /
t
XSRD
has been
met (if the previous state was self refresh).
2. This table describes alternate bank operation, except where noted, i.e., the current state is for bank n and the commands shown are
those allowed to be issued to bank m (assuming that bank m is in such a state that the given command is allowable). Exceptions are cov-
ered in the notes below.
3. Current state definitions:
Idle:
The bank has been precharged, and t
RP
has been met.
Row Active:
A row in the bank has been activated, and t
RCD
has been met. No data bursts/accesses and no register accesses are
in progress.
Read:
A Read burst has been initiated, with Auto Precharge disabled, and has not yet terminated or been terminated.
Write:
A Write burst has been initiated, with Auto Precharge disabled, and has not yet terminated or been terminated.
Read with Auto Precharge Enabled: See note 10.
Write with Auto Precharge Enabled: See note 10.
4. Auto Refresh and Mode Register Set commands may only be issued when all banks are idle.
5. A Burst Terminate command cannot be issued to another bank; it applies to the bank represented by the current state only.
6. All states and sequences not shown are illegal or reserved.
7. Reads or Writes listed in the Command/Action column include Reads or Writes with Auto Precharge enabled and Reads or Writes with
Auto Precharge disabled.
8. Requires appropriate DM masking.
9. A Write command may be applied after the completion of data output.
10. The Read with Auto Precharge enabled or Write with Auto Precharge enabled states can each be broken into two parts: the access
period and the precharge period. For Read with Auto Precharge, the precharge period is defined as if the same burst was executed with
Auto Precharge disabled and then followed with the earliest possible Precharge command that still accesses all of the data in the burst.
For Write with Auto Precharge, the precharge period begins when t
WR
ends, with t
WR
measured as if Auto Precharge was disabled. The
access period starts with registration of the command and ends where the precharge period (or t
RP
) begins. During the precharge period
of the Read with Auto Precharge Enabled or Write with Auto Precharge Enabled states, Active, Precharge, Read, and Write commands
to the other bank may be applied; during the access period, only Active and Precharge commands to the other bank may be applied. In
either case, all other related limitations apply (e.g. contention between Read data and Write data must be avoided).
相关PDF资料 |
PDF描述 |
|---|---|
| NT5DS32M8AT-6 | 256Mb DDR333/300 SDRAM |
| NT5DS32M8AT-66 | 256Mb DDR333/300 SDRAM |
| NT5SV16M16AT | 256Mb Synchronous DRAM |
| NT5SV16M16AT-75B | 256Mb Synchronous DRAM |
| NT5SV16M16AT-75BL | 256Mb Synchronous DRAM |
相关代理商/技术参数 |
参数描述 |
|---|---|
| NT5DS32M8AT-6 | 制造商:未知厂家 制造商全称:未知厂家 功能描述:256Mb DDR333/300 SDRAM |
| NT5DS32M8AT-66 | 制造商:未知厂家 制造商全称:未知厂家 功能描述:256Mb DDR333/300 SDRAM |
| NT5DS32M8AT-75B | 制造商:未知厂家 制造商全称:未知厂家 功能描述:256Mb Double Data Rate SDRAM |
| NT5DS32M8AT-7K | 制造商:未知厂家 制造商全称:未知厂家 功能描述:256Mb Double Data Rate SDRAM |
| NT5DS32M8AT-8B | 制造商:未知厂家 制造商全称:未知厂家 功能描述:256Mb Double Data Rate SDRAM |
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