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参数资料
| 型号： | NT5DS32M8AW-66 |
| 厂商： | Electronic Theatre Controls, Inc. |
| 英文描述： | 256Mb DDR333/300 SDRAM |
| 中文描述： | 256Mb的DDR333/300内存 |
| 文件页数： | 24/27页 |
| 文件大小： | 269K |
| 代理商： | NT5DS32M8AW-66 |
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NT5DS64M4AT NT5DS64M4AW
NT5DS32M8AT NT5DS32M8AW
256Mb DDR333/300 SDRAM
Preliminary
10/01
24
NANYA TECHNOLOGY CORP
. All rights reserved.
NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.
Electrical Characteristics & AC Timing - Absolute Specifications
Notes
1. Input slew rate = 1V/ns.
2. The CK/CK input reference level (for timing reference to CK/CK) is the point at which CK and CK cross:
the input reference level for signals other than CK/CK, is V
REF.
3. Inputs are not recognized as valid until V
REF
stabilizes.
4. The Output timing reference level, as measured at the timing reference point indicated in AC Characteristics (Note 3) is V
TT
.
5. t
HZ
and t
LZ
transitions occur in the same access time windows as valid data transitions. These parameters are not referred
to a specific voltage level, but specify when the device is no longer driving (HZ), or begins driving (LZ).
6. The maximum limit for this parameter is not a device limit. The device operates with a greater value for this parameter, but
system performance (bus turnaround) degrades accordingly.
7. The specific requirement is that DQS be valid (high, low, or some point on a valid transition) on or before this CK edge. A
valid
transition is defined as monotonic and meeting the input slew rate specifications of the device. When no writes were prev-
iously in progress on the bus, DQS will be transitioning from Hi-Z to logic LOW. If a previous write was in progress, DQS
could be HIGH, LOW, or transitioning from high to low at this time, depending on t
DQSS
.
8. A maximum of eight Autorefresh commands can be posted to any given DDR SDRAM device.
9. For command/address input slew rate
≥
1.0V/ns. Slew rate is measured between V
OH
(AC) and V
OL
(AC).
10. For command/address input slew rate
≥
0.5V/ns and < 1.0V/ns. Slew rate is measured between V
OH
(AC) and V
OL
(AC).
11. CK/CK slew rates are
≥
1.0V/ns.
12. These parameters guarantee device timing, but they are not necessarily tested on each device, and they may be guara-
nteed by design or tester characterization.
13. For each of the terms in parentheses, if not already an integer, round to the next highest integer. t
CK
is equal to the actual
system clock cycle time.
相关PDF资料 |
PDF描述 |
|---|---|
| NT5DS64M4AT | 256Mb DDR333/300 SDRAM |
| NT5DS64M4AT-6 | 256Mb DDR333/300 SDRAM |
| NT5DS64M4AT-66 | 256Mb DDR333/300 SDRAM |
| NT5DS64M4AW | 256Mb DDR333/300 SDRAM |
| NT5DS64M4AW-6 | 256Mb DDR333/300 SDRAM |
相关代理商/技术参数 |
参数描述 |
|---|---|
| NT5DS32M8AW-75B | 制造商:未知厂家 制造商全称:未知厂家 功能描述:256Mb Double Data Rate SDRAM |
| NT5DS32M8AW-7K | 制造商:未知厂家 制造商全称:未知厂家 功能描述:256Mb Double Data Rate SDRAM |
| NT5DS32M8AW-8B | 制造商:未知厂家 制造商全称:未知厂家 功能描述:256Mb Double Data Rate SDRAM |
| NT5DS32M8CS | 制造商:NANOAMP 制造商全称:NANOAMP 功能描述:256Mb DDR Synchronous DRAM |
| NT5DS32M8CS-5T | 制造商:NANOAMP 制造商全称:NANOAMP 功能描述:256Mb DDR Synchronous DRAM |
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