NT5SV64M4AT(L)
NT5SV32M8AT(L)
NT5SV16M16AT(L)
256Mb Synchronous DRAM
REV 1.0
May, 2001
14
NANYA TECHNOLOGY CORP
. All rights reserved.
NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.
Burst Write Command
The Burst Write command is initiated by having CS, CAS, and WE low while holding RAS high at the rising edge of the clock.
The address inputs determine the starting column address. There is no CAS latency required for burst write cycles. Data for the
first burst write cycle must be applied on the DQ pins on the same clock cycle that the Write Command is issued. The remaining
data inputs must be supplied on each subsequent rising clock edge until the burst length is completed. When the burst has fin-
ished, any additional data supplied to the DQ pins will be ignored.
Write Interrupted by a Write
A burst write may be interrupted before completion of the burst by another Write Command. When the previous burst is inter-
rupted, the remaining addresses are overridden by the new address and data will be written into the device until the pro-
grammed burst length is satisfied.
Burst Write Operation
Write Interrupted by a Write
COMMAND
NOP
WRITE A
NOP
NOP
NOP
NOP
NOP
NOP
DQs
DIN A
0
DIN A
1
DIN A
2
DIN A
3
NOP
CK
T0
T2
T1
T3
T4
T5
T6
T7
T8
Extra data is masked.
The first data element and the Write
are registered on the same clock edge.
(
Burst Length = 4, CAS latency = 2, 3)
: “H” or “L”
COMMAND
NOP
WRITE A
WRITE B
NOP
NOP
NOP
NOP
NOP
DQs
DIN A
0
DIN B
0
DIN B
1
DIN B
2
NOP
DIN B
3
CK
T0
T2
T1
T3
T4
T5
T6
T7
T8
1 CK Interval
(Burst Length = 4, CAS latency = 2, 3)