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参数资料
| 型号： | NTE834 |
| 厂商： | NTE Electronics, Inc. |
| 英文描述： | Integrated Circuit Low Power Low Offset Voltage Comparator |
| 中文描述： | 集成电路低功耗低失调电压比较器 |
| 文件页数： | 2/3页 |
| 文件大小： | 26K |
| 代理商： | NTE834 |
Electrical Characteristics:
(V
+
= 5V,
–
55
°
C
≤
T
A
≤
+125
°
C, unless otherwise specified)
Parameter
Test Conditions
Input Offset Voltage
T
A
= +25
°
C, Note 6
Input Bias Current
I
IN(+)
or I
IN(
–
)
with Output in Linear Range,
T
A
= +25
°
C, Note 4
Input Offset Current
I
IN(+)
–
I
IN(
–
)
, T
A
= +25
°
C
Input Common
–
Mode Voltage
Range
Supply Current
R
L
=
∞
on all Comparators, T
A
= +25
°
C
Voltage Gain
R
L
≥
15k
, V
+
= 15V (To Support Large
V
O
Swing), T
A
= +25
°
C
Large Signal Response Time
V
IN
= TTL Logic Swing, V
REF
= 1.4V,
V
RL
= 5V, R
L
= 5.1k
,
T
A
= +25
°
C
Response Time
V
RL
= 5V, R
L
= 5.1k
, T
A
= +25
°
C
Output Sink Current
V
IN(
–
)
≥
1V, V
IN(+)
= 0, V
O
≤
1.5V,
T
A
= +25
°
C
Saturation Voltage
V
IN(
–
)
≥
1V, V
IN(+)
= 0, I
SINK
≤
4mA,
T
A
= +25
°
C
Output Leakage Current
V
IN(+)
≥
1V, V
IN(
–
)
= 0, V
O
= 5V,
T
A
= +25
°
C
Input Offset Voltage
Note 6
Input Offset Current
I
IN(+)
–
I
IN(
–
)
Input Bias Current
I
IN(+)
or I
IN(
–
)
with Output in Linear Range
Input Common Mode Voltage
Range
Saturation Voltage
V
IN(
–
)
≥
1V, V
IN(+)
= 0, I
SINK
≤
4mA
Output Leakage Current
V
IN(+)
≥
1V, V
IN(
–
)
= 0, V
O
= 30V
Differential Input Voltage
All V
IN
’
s
≥
0V (or V
–
, if used)
Min
–
–
Typ
±
2.0
25
Max
±
5.0
250
Unit
mV
nA
–
0
±
5.0
–
±
50
nA
V
T
A
= +25
°
C, Note 5
V
+
–
1.5
–
–
0.8
200
2.0
–
mA
V/mV
–
300
–
ns
–
1.3
16
–
–
μ
s
mA
6.0
–
250
400
mV
–
0.1
–
nA
–
–
–
0
–
–
–
–
9.0
±
150
400
V
+
–
2.0
mV
DC
nA
nA
V
–
–
–
–
–
–
700
1.0
36
mV
μ
A
V
Note 1 For operating at high temperatures, these devices must be derated based on a +125
°
C maxi-
mum junction temperature and a thermal resistance of +175
°
C/W which applies for the device
soldered to a printed circuit board, operating in ambient still air. The low bias dissipation and
the
“
ON
–
OFF
”
characteristic of the outputs keeps the chip dissipation very low (P
D
≤
100mW),
provided the output transistors are allowed to saturate.
Note 2 Short circuits from the output to V
+
can cause excessive heating and eventual destruction.
The maximum output current is approximately 20mA independent of the magnitude of V
+
.
Note 3 This input current will only exist when the voltage at any of the input leads is driven negative.
It is due to the collector
–
base junction of the input PNP transistors becoming forward biased
and thereby acting as input diode clamps.
Note 4 The direction of the input current is out of the IC due to the PNP input stage. This current
is essentially constant, independent of the state of the output so no loading change exists
on the reference to input lines.
Note 5 The input common
–
mode voltage or either input signal voltage should not be allowed to go
negative by more than 0.3V. The upper end of the common
–
mode voltage range is V
+
–
1.5V,
but either or both inputs can go to +30V without damage.
Note 6. At output switch point, V
O
1.4V, R
S
= 0
with V
+
from 5V; and over the full input common
–
mode range (0V to V+
–
1.5V).
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