- 您现在的位置：买卖IC网 > PDF目录363718 > NZ48F3L0QTY (Intel Corp.) StrataFlash Wireless Memory PDF资料下载
参数资料
| 型号： | NZ48F3L0QTY |
| 厂商： | Intel Corp. |
| 英文描述： | StrataFlash Wireless Memory |
| 中文描述： | 无线的StrataFlash存储器 |
| 文件页数： | 11/106页 |
| 文件大小： | 1272K |
| 代理商： | NZ48F3L0QTY |
第1页第2页第3页第4页第5页第6页第7页第8页第9页第10页当前第11页第12页第13页第14页第15页第16页第17页第18页第19页第20页第21页第22页第23页第24页第25页第26页第27页第28页第29页第30页第31页第32页第33页第34页第35页第36页第37页第38页第39页第40页第41页第42页第43页第44页第45页第46页第47页第48页第49页第50页第51页第52页第53页第54页第55页第56页第57页第58页第59页第60页第61页第62页第63页第64页第65页第66页第67页第68页第69页第70页第71页第72页第73页第74页第75页第76页第77页第78页第79页第80页第81页第82页第83页第84页第85页第86页第87页第88页第89页第90页第91页第92页第93页第94页第95页第96页第97页第98页第99页第100页第101页第102页第103页第104页第105页第106页
Intel StrataFlash Wireless Memory (L18)
Datasheet
Intel StrataFlash Wireless Memory (L18)
Order Number: 251902, Revision: 009
April 2005
11
2.0
Functional Overview
The Intel StrataFlash Wireless Memory (L18) provides read-while-write and read-while-erase
capability with density upgrades through 256-Mbit. This family of devices provides high
performance at low voltage on a 16-bit data bus. Individually erasable memory blocks are sized for
optimum code and data storage.
Each device density contains one parameter partition and several main partitions. The flash
memory array is grouped into multiple 8-Mbit or 16-Mbit partitions. By dividing the flash memory
into partitions, program or erase operations can take place at the same time as read operations.
Although each partition has write, erase, and burst read capabilities, simultaneous operation is
limited to write or erase in one partition while other partitions are in read mode. The Intel
StrataFlash Wireless Memory (L18) allows burst reads that cross partition boundaries. User
application code is responsible for ensuring that burst reads do not cross into a partition that is
programming or erasing.
Upon initial power up or return from reset, the device defaults to asynchronous page-mode read.
Configuring the Read Configuration Register enables synchronous burst-mode reads. In
synchronous burst mode, output data is synchronized with a user-supplied clock signal. A WAIT
signal provides easy CPU-to-flash memory synchronization.
In addition to the enhanced architecture and interface, the Intel StrataFlash Wireless Memory
(L18) incorporates technology that enables fast factory program and erase operations. Designed for
low-voltage systems, the Intel StrataFlash Wireless Memory (L18) supports read operations with
V
CC
at 1.8 volt, and erase and program operations with V
PP
at 1.8 V or 9.0 V. Buffered Enhanced
Factory Programming (Buffered EFP) provides the fastest flash array programming performance
with V
PP
at 9.0 volt, which increases factory throughput. With V
PP
at 1.8 V, VCC and VPP can be
tied together for a simple, ultra-low power design. In addition to voltage flexibility, a dedicated
V
PP
connection provides complete data protection when V
PP
is less than V
PPLK
.
A Command User Interface (CUI) is the interface between the system processor and all internal
operations of the Intel StrataFlash Wireless Memory (L18). An internal Write State Machine
(WSM) automatically executes the algorithms and timings necessary for block erase and program.
A Status Register indicates erase or program completion and any errors that may have occurred.
An industry-standard command sequence invokes program and erase automation. Each erase
operation erases one block. The Erase Suspend feature allows system software to pause an erase
cycle to read or program data in another block. Program Suspend allows system software to pause
programming to read other locations. Data is programmed in word increments.
The Intel StrataFlash Wireless Memory (L18) offers power savings through Automatic Power
Savings (APS) mode and standby mode. The device automatically enters APS following read-cycle
completion. Standby is initiated when the system deselects the device by deasserting CE# or by
asserting RST#. Combined, these features can significantly reduce power consumption.
The Intel StrataFlash Wireless Memory (L18)’s protection register allows unique flash device
identification that can be used to increase system security. Also, the individual Block Lock feature
provides zero-latency block locking and unlocking.
相关PDF资料 |
PDF描述 |
|---|---|
| NZ48F3L0QTZ | StrataFlash Wireless Memory |
| NZ48F4000L0YBQ0 | StrataFlash Wireless Memory |
| NZ48F4000L0YTQ0 | StrataFlash Wireless Memory |
| NZ48F400BBY | StrataFlash Wireless Memory |
| NZ48F400BBZ | StrataFlash Wireless Memory |
相关代理商/技术参数 |
参数描述 |
|---|---|
| NZ48F3L0QTZ | 制造商:INTEL 制造商全称:Intel Corporation 功能描述:StrataFlash Wireless Memory |
| NZ48F4000L0YBQ0 | 制造商:INTEL 制造商全称:Intel Corporation 功能描述:StrataFlash Wireless Memory |
| NZ48F4000L0YTQ0 | 制造商:INTEL 制造商全称:Intel Corporation 功能描述:StrataFlash Wireless Memory |
| NZ48F4000L0ZBQ0 | 制造商:INTEL 制造商全称:Intel Corporation 功能描述:1.8 Volt Intel StrataFlash㈢ Wireless Memory with 3.0-Volt I/O (L30) |
| NZ48F4000L0ZTQ0 | 制造商:INTEL 制造商全称:Intel Corporation 功能描述:1.8 Volt Intel StrataFlash㈢ Wireless Memory with 3.0-Volt I/O (L30) |
发布紧急采购，3分钟左右您将得到回复。