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| 型号： | OM11048 |
| 厂商： | NXP Semiconductors |
| 文件页数： | 19/74页 |
| 文件大小： | 0K |
| 描述： | BOARD LPCXPRESSO LPC1343 |
| 产品培训模块： | LPCXpresso |
| 标准包装： | 1 |
| 系列： | LPCXpresso |
| 类型： | MCU |
| 适用于相关产品： | LPC1343 |
| 所含物品： | 板，软件 |
| 其它名称： | 568-4947 |
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LPC1311_13_42_43
All information provided in this document is subject to legal disclaimers.
NXP B.V. 2012. All rights reserved.
Product data sheet
Rev. 5 — 6 June 2012
26 of 74
NXP Semiconductors
LPC1311/13/42/43
32-bit ARM Cortex-M3 microcontroller
Upon power-up, any chip reset, or wake-up from Deep power-down mode, the
LPC1311/13/42/43 use the IRC as the clock source. Software may later switch to one of
the other available clock sources.
7.18.1.2
System oscillator
The system oscillator can be used as the clock source for the CPU, with or without using
the PLL. On the LPC1342/43, the system oscillator must be used to provide the clock
source to USB.
The system oscillator operates at frequencies of 1 MHz to 25 MHz. This frequency can be
boosted to a higher frequency, up to the maximum CPU operating frequency, by the
system PLL.
7.18.1.3
Watchdog oscillator
The watchdog oscillator can be used as a clock source that directly drives the CPU, the
watchdog timer, or the CLKOUT pin. The watchdog oscillator nominal frequency is
programmable between 7.8 kHz and 1.7 MHz. The frequency spread over processing and
temperature is
±40 % (see also Table 16).
7.18.2 System PLL and USB PLL
The LPC1342/43 contain a system PLL and a dedicated PLL for generating the 48 MHz
USB clock. The LPC131x contain the system PLL only. The system and USB PLLs are
identical.
The PLL accepts an input clock frequency in the range of 10 MHz to 25 MHz. The input
frequency is multiplied up to a high frequency with a Current Controlled Oscillator (CCO).
The multiplier can be an integer value from 1 to 32. The CCO operates in the range of
156 MHz to 320 MHz, so there is an additional divider in the loop to keep the CCO within
its frequency range while the PLL is providing the desired output frequency. The output
divider may be set to divide by 2, 4, 8, or 16 to produce the output clock. The PLL output
frequency must be lower than 100 MHz. Since the minimum output divider value is 2, it is
insured that the PLL output has a 50 % duty cycle. The PLL is turned off and bypassed
following a chip reset and may be enabled by software. The program must configure and
activate the PLL, wait for the PLL to lock, and then connect to the PLL as a clock source.
The PLL settling time is 100
μs.
7.18.3 Clock output
The LPC1311/13/42/43 features a clock output function that routes the IRC oscillator, the
system oscillator, the watchdog oscillator, or the main clock to an output pin.
7.18.4 Wake-up process
The LPC1311/13/42/43 begin operation at power-up and when awakened from Deep
power-down mode by using the 12 MHz IRC oscillator as the clock source. This allows
chip operation to resume quickly. If the main oscillator or the PLL is needed by the
application, software will need to enable these features and wait for them to stabilize
before they are used as a clock source.
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