- 您现在的位置：买卖IC网 > PDF目录17167 > OM13008,598 (NXP Semiconductors)BOARD LPC XPRESSO LPC122X PDF资料下载
参数资料
| 型号： | OM13008,598 |
| 厂商： | NXP Semiconductors |
| 文件页数： | 43/61页 |
| 文件大小： | 0K |
| 描述： | BOARD LPC XPRESSO LPC122X |
| 产品培训模块： | LPC1200 Series for Industrial Control |
| 标准包装： | 1 |
| 系列： | LPCXpresso |
| 类型： | MCU |
| 适用于相关产品： | LPC122x，ARM Cortex-M0 |
| 所含物品： | 板 |
| 其它名称： | 568-6642 OM13008 |
第1页第2页第3页第4页第5页第6页第7页第8页第9页第10页第11页第12页第13页第14页第15页第16页第17页第18页第19页第20页第21页第22页第23页第24页第25页第26页第27页第28页第29页第30页第31页第32页第33页第34页第35页第36页第37页第38页第39页第40页第41页第42页当前第43页第44页第45页第46页第47页第48页第49页第50页第51页第52页第53页第54页第55页第56页第57页第58页第59页第60页第61页
LPC122X
All information provided in this document is subject to legal disclaimers.
NXP B.V. 2011. All rights reserved.
Product data sheet
Rev. 2 — 26 August 2011
48 of 61
NXP Semiconductors
LPC122x
32-bit ARM Cortex-M0 microcontroller
11.5 I2C-bus
[1]
Parameters are valid over operating temperature range unless otherwise specified.
[2]
tHD;DAT is the data hold time that is measured from the falling edge of SCL; applies to data in transmission and the acknowledge.
[3]
A device must internally provide a hold time of at least 300 ns for the SDA signal (with respect to the VIH(min) of the SCL signal) to
bridge the undefined region of the falling edge of SCL.
[4]
Cb = total capacitance of one bus line in pF. If mixed with Hs-mode devices, faster fall times are allowed.
[5]
The maximum tf for the SDA and SCL bus lines is specified at 300 ns. The maximum fall time for the SDA output stage tf is specified at
250 ns. This allows series protection resistors to be connected in between the SDA and the SCL pins and the SDA/SCL bus lines
without exceeding the maximum specified tf.
[6]
In Fast-mode Plus, fall time is specified the same for both output stage and bus timing. If series resistors are used, designers should
allow for this when considering bus timing.
[7]
The maximum tHD;DAT could be 3.45 s and 0.9 s for Standard-mode and Fast-mode but must be less than the maximum of tVD;DAT or
tVD;ACK by a transition time. This maximum must only be met if the device does not stretch the LOW period (tLOW) of the SCL signal. If
the clock stretches the SCL, the data must be valid by the set-up time before it releases the clock.
[8]
tSU;DAT is the data set-up time that is measured with respect to the rising edge of SCL; applies to data in transmission and the
acknowledge.
[9]
A Fast-mode I2C-bus device can be used in a Standard-mode I2C-bus system but the requirement tSU;DAT = 250 ns must then be met.
This will automatically be the case if the device does not stretch the LOW period of the SCL signal. If such a device does stretch the
LOW period of the SCL signal, it must output the next data bit to the SDA line tr(max) + tSU;DAT = 1000 + 250 = 1250 ns (according to the
Standard-mode I2C-bus specification) before the SCL line is released. Also the acknowledge timing must meet this set-up time.
Table 16.
Dynamic characteristic: I2C-bus pins
Symbol
Parameter
Conditions
Min
Max
Unit
fSCL
SCL clock frequency
Standard-mode
0
100
kHz
Fast-mode
0
400
kHz
Fast-mode Plus
0
1
MHz
tf
fall time
of both SDA and
SCL signals
Standard-mode
-300
ns
Fast-mode
20 + 0.1
C
b
300
ns
Fast-mode Plus
-
120
ns
tLOW
LOW period of the SCL clock
Standard-mode
4.7
-
s
Fast-mode
1.3
-
s
Fast-mode Plus
0.5
-
s
tHIGH
HIGH period of the SCL clock
Standard-mode
4.0
-
s
Fast-mode
0.6
-
s
Fast-mode Plus
0.26
-
s
tHD;DAT
data hold time
Standard-mode
0
-
s
Fast-mode
0
-
s
Fast-mode Plus
0
-
s
tSU;DAT
data set-up time
Standard-mode
250
-
ns
Fast-mode
100
-
ns
Fast-mode Plus
50
-
ns
相关PDF资料 |
PDF描述 |
|---|---|
| SP7122AEB | EVAL BOARD FOR SP7122A |
| LTC1558CGN-5#PBF | IC BACKUP BATT CNTRLR 5V 16-SSOP |
| SJ-3551 1" | DUAL LOCK PRESS 1"X25YD BLK 400 |
| LTC1558CS-3.3#PBF | IC BACKUP BATT CNTRLR3.3V 16SOIC |
| 0210490709 | CABLE JUMPER 1.25MM .127M 4POS |
相关代理商/技术参数 |
参数描述 |
|---|---|
| OM13009 | 制造商:NXP Semiconductors 功能描述:EVAL MOTOR CONTROL LPCXPRESSO 制造商:NXP Semiconductors 功能描述:LPC1114, MC, LPCXPRESSO, EVAL BOARD 制造商:NXP Semiconductors 功能描述:LPC1114, MC, LPCXPRESSO, EVAL BOARD; Silicon Manufacturer:NXP; Core Architecture:ARM; Core Sub-Architecture:Cortex-M0; Silicon Core Number:LPC11xx; Silicon Family Name:LPC11xx; Kit Contents:Board, LPC1114 Board, BLDC Motor, USB ;RoHS Compliant: Yes |
| OM13009,598 | 功能描述:KIT EVALUATION MOTOR CONTROL RoHS:是 类别:编程器，开发系统 >> 评估演示板和套件 系列:LPCXpresso 标准包装:1 系列:PSoC® 主要目的:电源管理，热管理 嵌入式:- 已用 IC / 零件:- 主要属性:- 次要属性:- 已供物品:板，CD，电源 |
| OM13009598 | 制造商:NXP Semiconductors 功能描述:EVAL MOTOR CONTROL LPCXPRESS |
| OM13010,598 | 功能描述:DEMO BOARD LPC1800 RoHS:否 类别:编程器，开发系统 >> 通用嵌入式开发板和套件（MCU、DSP、FPGA、CPLD等） 系列:Cortex-M3™, LPC1800 产品培训模块:Blackfin® Processor Core Architecture Overview Blackfin® Device Drivers Blackfin® Optimizations for Performance and Power Consumption Blackfin® System Services 特色产品:Blackfin? BF50x Series Processors 标准包装:1 系列:Blackfin® 类型:DSP 适用于相关产品:ADSP-BF548 所含物品:板，软件，4x4 键盘，光学拨轮，QVGA 触摸屏 LCD 和 40G 硬盘 配用:ADZS-BFBLUET-EZEXT-ND - EZ-EXTENDER DAUGHTERBOARDADZS-BFLLCD-EZEXT-ND - BOARD EXT LANDSCAP LCD INTERFACE 相关产品:ADSP-BF542BBCZ-4A-ND - IC DSP 16BIT 400MHZ 400CSBGAADSP-BF544MBBCZ-5M-ND - IC DSP 16BIT 533MHZ MDDR 400CBGAADSP-BF542MBBCZ-5M-ND - IC DSP 16BIT 533MHZ MDDR 400CBGAADSP-BF542KBCZ-6A-ND - IC DSP 16BIT 600MHZ 400CSBGAADSP-BF547MBBCZ-5M-ND - IC DSP 16BIT 533MHZ MDDR 400CBGAADSP-BF548BBCZ-5A-ND - IC DSP 16BIT 533MHZ 400CSBGAADSP-BF547BBCZ-5A-ND - IC DSP 16BIT 533MHZ 400CSBGAADSP-BF544BBCZ-5A-ND - IC DSP 16BIT 533MHZ 400CSBGAADSP-BF542BBCZ-5A-ND - IC DSP 16BIT 533MHZ 400CSBGA |
| OM13011 | 制造商:NXP Semiconductors 功能描述:EVAL KEIL MCB1200 制造商:NXP Semiconductors 功能描述:LPC1227, KEIL, SERIAL, EVAL BOARD 制造商:NXP Semiconductors 功能描述:; Silicon Manufacturer:NXP; Core Architecture:ARM; Core Sub-Architecture:Cortex-M0; Silicon Core Number:LPC12xx; Silicon Family Name:LPC122x; Features:Evaluation Board for LPC1227 Microcontroller ;RoHS Compliant: Yes |
发布紧急采购，3分钟左右您将得到回复。