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| 型号： | OM5156M |
| 厂商： | NXP SEMICONDUCTORS |
| 元件分类： | XO, clock |
| 英文描述： | Low-voltage dual frequency synthesizer for radio telephones |
| 中文描述： | PLL FREQUENCY SYNTHESIZER, 2000 MHz, PDSO20 |
| 封装： | 4.40 MM, PLASTIC, SOT-266-1, SSOP-20 |
| 文件页数： | 5/20页 |
| 文件大小： | 160K |
| 代理商： | OM5156M |
1995 Nov 24
5
Philips Semiconductors
Product specification
Low-voltage dual frequency
synthesizer for radio telephones
OM5156M
The reference and main divider outputs are connected to
a phase/frequency detector that controls two charge
pumps. The two pumps have a common bias-setting
current that is set by an external resistance. The ratio
between currents in fast and normal operating modes can
be programmed via the 3-wire serial bus. The low current
pump remains active except in power-down. The high
current pump is enabled via the control input FAST (pin 1).
By appropriate connection to the loop filter, dual bandwidth
loops are provided: short time constant during frequency
switching (FAST mode) to speed-up channel changes and
low bandwidth in the settled state (on-frequency) to reduce
noise and breakthrough levels.
The principal synthesizer speed-up charge pump (CPPF)
is controlled by the FAST input in synchronization with
phase detector operation in such a way that potential
disturbances are minimized. The dead zone (caused by
finite time taken to switch the current sources on or off) is
cancelled by feedback from the normal pump output to the
phase detector thereby improving linearity.
An open drain transistor drives the output pin LOCK
(pin 20). It is recommended that the pull-up resistor from
this pin to V
DD
is chosen such that the value is high enough
to keep the sink current in the LOW state below 400
μ
A.
The circuit can be programmed to output either the phase
error in the principal or auxiliary phase detectors or the
combination from both detectors (OR function). The
resultant output will be a current pulse with the duration of
the selected phase error. By appropriate external filtering
and threshold comparison, an out-of-lock or an in-lock flag
is generated.
Auxiliary synthesizer
The auxiliary synthesizer has a 14-bit main divider and an
11-bit reference divider. A separate power-down input
AOFF (pin 19), disables currents in the auxiliary dividers,
phase detector, and charge pump. The auxiliary input
signal is amplified and fed to the main divider. The input
buffer presents a high impedance, dominated by pin and
pad capacitance. First divider stages use bipolar
technology operating at input frequencies up to 300 MHz;
the slower bits are CMOS. The auxiliary loop phase
detector and charge pump use similar circuits to the main
loop low-current phase comparator, including dead-zone
compensation feedback.
The auxiliary reference divider is clocked on the opposite
edge of the principal reference divider to ensure that active
edges arrive at the auxiliary and principal phase detectors
at different times. This minimizes the potential for
interference between the charge pumps of each loop.
Serial programming bus
A simple 3-line unidirectional serial bus is used to program
the circuit. The 3 lines are DATA, CLK and E (enable).
The data sent to the device is loaded in bursts framed by
E. Programming clock edges and their appropriate data
bits are ignored untilE goes active LOW. The programmed
information is loaded into the addressed latch when E
returns inactive HIGH. Only the last 21 bits serially clocked
into the device are retained within the programming
register. Additional leading bits are ignored, and no check
is made on the number of clock pulses. The fully static
CMOS design uses virtually no current when the bus is
inactive. It can always capture new programmed data
even during power-down of main and auxiliary loops.
However when either principal synthesizer or auxiliary
synthesizer or both are powered-on, the presence of a
TCXO signal is required at pin 8 (f
XTAL
) for correct
programming.
Data format
Data is entered with the most significant bit first. The
leading bits make up the data field, while the trailing four
bits are an address field. The OM5156M uses 5 of the
16 available addresses. The data format is shown in
Table 1. The first entered bit is p1, the last bit is p21.
The trailing address bits are decoded on the inactive edge
of E. This produces an internal load pulse to store the data
in one of the addressed latches. To ensure that the data is
correctly loaded on first power-up, E should be held LOW
and only taken HIGH after having programmed an
appropriate register. To avoid erroneous divider ratios, the
pulse is not allowed during data reads by the frequency
dividers.
This condition is guaranteed by respecting a minimum E
pulse width after data transfer. The corresponding
relationship between data fields and addresses is given in
Table 2.
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