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参数资料
型号： ORSO82G5-3F680C
厂商： Lattice Semiconductor Corporation
文件页数： 103/153页
文件大小： 0K
描述： IC FPSC TRANSCEIVER 8CH 680-BGA
产品变化通告： Product Discontinuation 01/Aug/2011
标准包装： 24
系列： *
Lattice Semiconductor
ORCA ORSO42G5 and ORSO82G5 Data Sheet
53
Figure 39. OPC2 and OPC8 Block Diagrams
TX FIFO Block
In cell mode, the TXFIFO block contains the write state machine and FIFO memory. The FIFO is used to retime the
cell data from the FPGA interface at a rate of 156 MHz to the framer rate of 77.76 MHz.
The FIFO memory is implemented as a 64 x 34 FIFO. The FIFO receives data as 33-bit words with the start-of-cell
as the MSB of each word. Thus each cell occupies a maximum size of 23 words. For each link, the memory must
be capable of holding at least 2 cells or 46 words (one for write and one for read). To ensure extra space, this
capacity has been increased to 64 words. In addition, an extra bit has been reserved to store the link idle cell indi-
cator bit which is used for indicating the internally generated idle cells. Thus each word in a cell is 34 bits. Data are
written to the memory on the 156 MHz clock domain and read on the 77.76 MHz clock domain by the
Tx_Frame_Processor block. The OPC requires no response from the TXFIFO for writing data. The TXFIFO is guar-
anteed by design to not overow or underrun with correct clocking.
TX Frame Processor
The Tx_Frame_Processor (TFP) block is the primary data processing block in the both SONET mode and cell
mode. It organizes the cell data into a SONET frame before sending it to the SERDES. In cell mode, the 32-bit data
comes from the TX FIFO block. The three major TFP sub-blocks were described in the SONET mode section.
In cell mode, the Payload sub block is activated by the link_frm_sync in cell mode. A pulse on this signal from the
OPC indicates the start of a frame. Each frame contains 4 different types of bytes in cell mode:
TOH bytes (Auto TOH mode only)
Link Header (LH) bytes
Cell payload bytes
Pad bytes
TX
FIFO
OPC2
Block
OPC2_[A:B][1:2][39:0]
SYSCLK156[A:B][1:2]
32
77.76 MHz
TX
FIFO
32
77.76 MHz
TX
FIFO
OPC8
OPC8[159:0]
SYSCLK156 8
32
77.76 MHz
TX
FIFO
32
77.76 MHz
LINK 0
LINK 1
LINK 0
LINK 7
40
160
FPGA
LOGIC
Block
FPGA
LOGIC
(ORSO82G5
only)
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ORSO82G5-3FN680C 功能描述:FPGA - 现场可编程门阵列 ORCA FPSC 1.5V 2.7 G b Bpln Xcvr 643K Gt RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 栅极数量: 逻辑块数量:943 内嵌式块RAM - EBR:1956 kbit 输入/输出端数量:128 最大工作频率:800 MHz 工作电源电压:1.1 V 最大工作温度:+ 70 C 安装风格:SMD/SMT 封装 / 箱体:FBGA-256
ORSO82G5-3FN680C1 功能描述:FPGA - 现场可编程门阵列 10368 LUT 372 I/O RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 栅极数量: 逻辑块数量:943 内嵌式块RAM - EBR:1956 kbit 输入/输出端数量:128 最大工作频率:800 MHz 工作电源电压:1.1 V 最大工作温度:+ 70 C 安装风格:SMD/SMT 封装 / 箱体:FBGA-256
ORSO82G5-G2-PAC-EV 功能描述:可编程逻辑 IC 开发工具 ORCA ORSO82G5-FPSC Eval Brd RoHS:否 制造商:Altera Corporation 产品:Development Kits 类型:FPGA 工具用于评估:5CEFA7F3 接口类型: 工作电源电压:
ORSPI4 制造商:LATTICE 制造商全称:Lattice Semiconductor 功能描述:Dual SPI4 Interface and High-Speed SERDES FPSC
ORSPI4-1F1156C 功能描述:FPGA - 现场可编程门阵列 16192 LUT RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 栅极数量: 逻辑块数量:943 内嵌式块RAM - EBR:1956 kbit 输入/输出端数量:128 最大工作频率:800 MHz 工作电源电压:1.1 V 最大工作温度:+ 70 C 安装风格:SMD/SMT 封装 / 箱体:FBGA-256
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