参数资料
| 型号： | P0006 |
| 厂商： | Terasic Technologies Inc |
| 文件页数： | 16/26页 |
| 文件大小： | 0K |
| 描述： | BOARD ADAPTER THDB-SUM |
| 标准包装： | 1 |
| 附件类型： | 适配器板 |
| 适用于相关产品： | 带 HSMC 连接器的线路板 |
| 产品目录页面： | 607 (CN2011-ZH PDF) |
| 相关产品： | P0528-ND - BOARD DEV DE1 ALTERA P0304-ND - DE2-70 CALL FOR ACADEMIC PRICING P0301-ND - DE2 CALL FOR ACADEMIC PRICING |
Board Components
3.3 USB On-The-Go transceiver
This section describes the USB On-The-Go transceiver on the THDB-SUM board
The THDB-SUM is equipped with a NXP ISP1504C USB On-The-Go transceiver (U11) and Mini USB AB type
receptacle connector (J8) to provide USB interface to the HSMC interface host board. The ISP1504 is a
Universal Serial Bus (USB) On-The-Go (OTG) transceiver that is fully compliant with Universal Serial Bus
Specification Rev. 2.0, On-The-Go Supplement to the USB 2.0 Specification Rev. 1.3 and UTMI+ Low Pin
Interface (ULPI) Specification Rev. 1.1.
The pervious section, Santa Cruz Connector, has mentioned that USB transceiver and Santa Cruz connector
share the I/Os which connect to HSMC connector, which means users can only choose one function between
USB and Satan Cruz interface, If users would like to choose the function of USB transceiver, please turn on
JP2. For more detailed information about this transceiver, please refer to the datasheet which can be found in
the NXP’s website.
In addition, for OTG implementations, a 2-pin header named JP1 is connected with ID (identification) pin of
the USB OTG transceiver and micro-USB receptacle. As shown in Figure 3.8 , The logic level of the ID pin on
the USB OTG transceiver can be configured to logic high or low via JP1. As defined in On-The-Go supplement
to the USB 2.0 specification Rev. 1.3, the ID pin dictates the initial role of the link. If ID is detected as HIGH,
the link must assume the role of a peripheral. If ID is detected as LOW, the link must assume a
host role. Table 3.7 shows the JP1 configuration setting for the ID.
Finally, the detailed pin mappings between the USB On-The-Go transceiver and the HSMC connector are
shown in Table3.8 .
Table 3.7 The configuration of the ID pin
JP2 setting
Open
Close
Host or peripheral role
Peripheral
Host
14
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