参数资料
型号: P0307
厂商: Terasic Technologies Inc
文件页数: 12/39页
文件大小: 0K
描述: KIT DEV 4.3" LCD TOUCH PANEL
标准包装: 1
附件类型: NTSC/PAL TV 播放器
适用于相关产品: DE2,DE1
产品目录页面: 607 (CN2011-ZH PDF)
相关产品: P0528-ND - BOARD DEV DE1 ALTERA
P0304-ND - DE2-70 CALL FOR ACADEMIC PRICING
P0301-ND - DE2 CALL FOR ACADEMIC PRICING
其它名称: TRDB_LTM
Using the LTM
3-2 Input timing of the LCD panel display function
This section will describe the timing specification of the LCD synchronous signals and
RGB data.
To determine the sequencing and the timing of the image signals displayed on the LCD panel, the
corresponding synchronous signals from FPGA to the LCD panel should follow the timing
specification.
Figure 3.2 illustrates the basic timing requirements for each row (horizontal) that is displayed on
the LCD panel. An active-low pulse of specific duration (time t hpw in the figure) is applied to the
horizontal synchronization (HD) input of the LCD panel, which signifies the end of one row of data
and the start of the next. The data (RGB) inputs on the LCD panel are not valid for a time period
called the hsync back porch ( t hbp ) after the hsync pulse occurs, which is followed by the display
area ( t hd ). During the data display area the RGB data drives each pixel in turn across the row
being displayed. Also, during the period of the data display area, the data enable signal (DEN)
must be driven to logic high. Finally, there is a time period called the hsync front porch ( t hfp ) where
the RGB signals are not valid again before the next hsync pulse can occur.
The timing of the vertical synchronization (VD) is the same as shown in Figure 3.3, except that a
vsync pulse signifies the end of one frame and the start of the next, and the data refers to the set
of rows in the frame (horizontal timing). Table 3.2 and 3.3 show for different resolutions, the
durations of time periods t hpw , t hbp , t hd , and t hfp for both horizontal and vertical timing. Finally, the
timing specification of the synchronous signals is shown in the Table 3.4.
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