参数资料
| 型号： | P1010NXN5FFA |
| 厂商： | Freescale Semiconductor |
| 文件页数： | 2/2页 |
| 文件大小： | 0K |
| 描述： | IC MPU 800MHZ 425TEPBGA1 |
| 产品培训模块： | Securing Intelligent Industrial and Network Devices |
| 产品变化通告： | ESDHC Host Detect Change 13/Feb/2012 |
| 标准包装： | 1 |
| 系列： | QorIQ P1 |
| 处理器类型： | e500 |
| 速度： | 800MHz |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 425-FBGA |
| 供应商设备封装： | 425-TEPBGA1 |
| 包装： | 托盘 |
For more information about QorIQ products, visit freescale.com/QorIQ
Freescale, the Freescale logo, PowerQUICC and QorIQ are trademarks of Freescale Semiconductor, Inc., Reg. U.S. Pat. & Tm. Off.
All other product or service names are the property of their respective owners. The Power Architecture and Power.org word marks
and the Power and Power.org logos and related marks are trademarks and service marks licensed by Power.org.
2010, 2013 Freescale Semiconductor, Inc.
Document Number: QP1010FS REV 1
Security Engine
The QorIQ security engine (SEC) is optimized
to handle all the algorithms associated with
IPSec, IEEE Std. 802.11i standard, and iSCSI.
The security engine also supports booting to a
known good state, untamperable boot code,
key storage, I/O protection, and secure debug.
The SEC is a modular and scalable security
core optimized to process all the algorithms
associated with IPsec, IKE, SSL/TLS,
iSCSI, SRTP, IEEE Std. 802.11i, IEEE Std.
802.16 (WiMAX), and IEEE Std. 802.1AE
(MACSec). The SEC is designed to perform
multi-algorithmic operations (for example,
3DES-HMAC-SHA-1) in a single pass of the
data. The security coprocessor in the QorIQ
P1010 processor is capable of performing
single-pass security cryptographic processing
for SSL 3.0, SSL 3.1/TLS 1.0, IPSec, SRTP,
and IEEE Std. 802.11i.
SEC Features
XOR engine for parity checking in RAID
storage applications
Four crypto-channels, each supporting
multi-command descriptor chains
Cryptographic Execution Units:
PKHA (public key hardware accelerator)
DESA (DES accelerator)
AESA (AES accelerator)
MDHA (message digest hardware
accelerator)
RNG (random number generator)
AFHA (ARC four hardware accelerator)
STHA (SNOW 3G f8 and f9 hardware
accelerators)
CRCA (cyclic redundancy check
accelerator)
KFHA (Kasumi hardware accelerator)
Dual FlexCAN controllers
Two FlexCAN (revision 2.0B) controllers provide
a standard interface for implementing industrial
protocols. Each FlexCAN controller has the
following features:
Programmable bit rates up to 1 Mb/s
Standard data and remote frames
Extended data and remote frames
Up to eight bytes data length
Up to 64 message buffers (MB), each
configurable as Rx or Tx
Individual Rx mask registers per message
buffers
Rx FIFO with storage capacity of six frames
and internal pointer handling
Rx FIFO ID filtering
Time stamp based on 16-bit free running
timer
Technical Specifications
Single e500 core, built on Power
Architecture technology
36-bit physical addressing
Double-precision floating-point support
32 KB L1 instruction cache and 32 KB
L1 data cache
533 MHz to 800 MHz core clock
frequency
256 KB L2 cache with ECC, also
configurable as SRAM and stashing
memory
Three 10/100/1000 Mb/s enhanced three-
speed Ethernet controllers (eTSECs)
TCP/IP acceleration and classification
capabilities
IEEE 1588 support
Lossless flow control
RGMII, SGMII
High-speed interfaces (not all available
simultaneously)
Six SerDes to 3.125 GHz multiplexed
across controllers
Two PCI Express controllers
Two SGMII interfaces
Two SATA interfaces
One USB controller (USB 2.0) with
integrated PHY, host, OTG and device
support
Serial peripheral interface
Trusted boot platform, integrated security
engine (SEC 4.0)
Crypto algorithm support includes
3DES, AES, RSA/ECC, MD5/
SHA, ARC4, Snow 3G and FIPS
deterministic RNG
Single pass encryption/message
authentication for common security
protocols (IPsec, SSL, SRTP, WiMAX)
XOR acceleration
16/32-bit DDR3/DDR3L SDRAM memory
controller with ECC support
Four-channel DMA controller
Two I2C controllers, two DUARTs, timers
Integrated flash controller with enhanced
capabilities to support large pages
32 general-purpose I/O signals
Package: 425-pin TEPBGA1, 0.8 mm pitch,
19 mm x 19 mm
Software and Tools Support
Enea: Real-time operating system support
Green Hills: Complete portfolio of
software and hardware development tools,
trace tools and real-time operating systems
Mentor Graphics: Commercial grade Linux
solution
P1010 reference design board (RDB)
QorIQ P1010 and P1014 Comparison
QorIQ Device
Top Core Frequency
L2 Size
DDR 3 Support
GE Ports
SATA
PCI Express
Security
CAN
P1010
1000 MHz
256 KB
16/32-bit @ 800 MHz
3
2
Trusted
2
P1014
800 MHz
256 KB
16-bit @ 800 MHz
2
No
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相关代理商/技术参数 |
参数描述 |
|---|---|
| P1010NXN5FHA | 制造商:Freescale Semiconductor 功能描述:P1010 IND EXT NE 667/800 - Bulk |
| P1010NXN5HFA | 功能描述:处理器 - 专门应用 P1010 IND EXT NE 800/667 RoHS:否 制造商:Freescale Semiconductor 类型:Multimedia Applications 核心:ARM Cortex A9 处理器系列:i.MX6 数据总线宽度:32 bit 最大时钟频率:1 GHz 指令/数据缓存: 数据 RAM 大小:128 KB 数据 ROM 大小: 工作电源电压: 最大工作温度:+ 95 C 安装风格:SMD/SMT 封装 / 箱体:MAPBGA-432 |
| P1010NXN5HHA | 功能描述:处理器 - 专门应用 P1010 IND EXT NE 800/800 RoHS:否 制造商:Freescale Semiconductor 类型:Multimedia Applications 核心:ARM Cortex A9 处理器系列:i.MX6 数据总线宽度:32 bit 最大时钟频率:1 GHz 指令/数据缓存: 数据 RAM 大小:128 KB 数据 ROM 大小: 工作电源电压: 最大工作温度:+ 95 C 安装风格:SMD/SMT 封装 / 箱体:MAPBGA-432 |
| P1010PSE5DFA | 功能描述:处理器 - 专门应用 P1010E Proto 533/667 (pre-qual sample) RoHS:否 制造商:Freescale Semiconductor 类型:Multimedia Applications 核心:ARM Cortex A9 处理器系列:i.MX6 数据总线宽度:32 bit 最大时钟频率:1 GHz 指令/数据缓存: 数据 RAM 大小:128 KB 数据 ROM 大小: 工作电源电压: 最大工作温度:+ 95 C 安装风格:SMD/SMT 封装 / 箱体:MAPBGA-432 |
| P1010PSE5FFA | 功能描述:处理器 - 专门应用 P1010E Proto 667/667 (pre-qual sample) RoHS:否 制造商:Freescale Semiconductor 类型:Multimedia Applications 核心:ARM Cortex A9 处理器系列:i.MX6 数据总线宽度:32 bit 最大时钟频率:1 GHz 指令/数据缓存: 数据 RAM 大小:128 KB 数据 ROM 大小: 工作电源电压: 最大工作温度:+ 95 C 安装风格:SMD/SMT 封装 / 箱体:MAPBGA-432 |
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