P2042A
LCD Panel EMI Reduction IC
2010 SCILLC. All rights reserved.
Publication Order Number:
November 2012 – Rev. 4
P2042/D
Features
FCC approved method of EMI attenuation
Provides up to 15dB of EMI suppression
Generates a low EMI spread spectrum clock of the
input frequency
Input frequency range: 30MHz -110MHz.
Output frequency range: 30MHz -110MHz
Optimized for 32.5MHz, 54MHz, 65MHz, 74MHz and
108MHz pixel clock frequencies
Internal loop filter minimizes external components and
board space
Eight selectable high spread ranges up to ±2%
Selectable Center Spread options
SSON# control pin for spread spectrum enable and
disable options
Low cycle-to-cycle jitter
3.3V ± 0.3V operating range
CMOS design
Supports most mobile graphic accelerator and LCD
timing controller specifications
Available in 8-pin TSSOP Package
Product Description
The P2042A is a versatile spread spectrum frequency
modulator designed specifically for digital flat panel
applications.
The
P2042A
reduces
electromagnetic
interference (EMI) at the clock source, allowing system
wide reduction of EMI of down stream clock and data
dependent signals. The P2042A allows significant system
cost savings by reducing the number of circuit board
layers
ferrite
beads,
shielding
and
other
passive
components that are traditionally required to pass EMI
regulations.
The P2042A uses the most efficient and optimized
modulation
profile
approved
by
the
FCC
and
is
implemented in a proprietary all digital method.
The P2042A modulates the output of a single PLL in order
to “spread” the bandwidth of a synthesized clock, and
more importantly, decreases the peak amplitudes of its
harmonics. This results in significantly lower system EMI
compared to the typical narrow band signal produced by
oscillators and most frequency generators. Lowering EMI
by increasing a signal’s bandwidth is called ‘spread
spectrum clock generation’.
Applications
The
P2042A is
targeted
towards
digital flat panel
applications for notebook PCs, palm-size PCs, office
automation equipments and LCD monitors.
Block Diagram
VSS
Frequency
Divider
Feedback
Divider
Modulation
Phase
Detector
Loop
Filter
VCO
Output
Divider
PLL
VDD
SSON#
SR0 CP1 CP0
ModOUT
CLKIN