参数资料
型号: P4C1256L-45CMBLF
厂商: PYRAMID SEMICONDUCTOR CORP
元件分类: DRAM
英文描述: HIGH SPEED 32K x 8 STATIC CMOS RAM
中文描述: 32K X 8 STANDARD SRAM, 45 ns, CDIP28
封装: 0.300 INCH, ROHS COMPLIANT, CERAMIC, SIDE BRAZED, DIP-28
文件页数: 5/17页
文件大小: 183K
代理商: P4C1256L-45CMBLF
P4C1256
Page 5 of 17
Document #
SRAM119
REV G
TIMING WAVEFORM OF READ CYCLE NO. 2 (ADDRESS CONTROLLED)
(5,6)
TIMING WAVEFORM OF READ CYCLE NO. 3 (
CE
CONTROLLED)
(5,7)
Notes:
1. Stresses greater than those listed under MAXIMUM RATINGS may
cause permanent damage to the device. This is a stress rating only
and functional operation of the device at these or any other conditions
above those indicated in the operational sections of this specification
is not implied. Exposure to MAXIMUM rating conditions for extended
periods may affect reliability.
2. Extended temperature operation guaranteed with 400 linear feet per
minute of air flow.
3. Transient inputs with V
and I
not more negative than –3.0V and
–100mA, respectively, are permissible for pulse widths up to 20 ns.
4. This parameter is sampled and not 100% tested.
5.
WE
is HIGH for READ cycle.
6.
CE
is LOW and
OE
is LOW for READ cycle.
7. ADDRESS must be valid prior to, or coincident with
CE
8. Transition is measured ± 200 mV from steady state voltage prior to
change, with loading as specified in Figure 1. This parameter is
sampled and not 100% tested.
9. Read Cycle Time is measured from the last valid address to the first
transitioning address.
transition LOW.
TIMING WAVEFORM OF READ CYCLE NO. 1 (
OE
CONTROLLED)
(5)
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