- 您现在的位置：买卖IC网 > PDF目录299585 > P4C1256L-70PILF (PYRAMID SEMICONDUCTOR CORP) 32K X 8 STANDARD SRAM, 70 ns, PDIP28 PDF资料下载
参数资料
| 型号： | P4C1256L-70PILF |
| 厂商： | PYRAMID SEMICONDUCTOR CORP |
| 元件分类： | SRAM |
| 英文描述： | 32K X 8 STANDARD SRAM, 70 ns, PDIP28 |
| 封装： | 0.300 INCH, ROHS COMPLIANT, PLASTIC, DIP-28 |
| 文件页数： | 12/16页 |
| 文件大小： | 1155K |
| 代理商： | P4C1256L-70PILF |
W39L040
Publication Release Date: April 14, 2005
- 5 -
Revision A6
The manufacturer and device codes may also be read via the command register, for instance, when
the W39L040 is erased or programmed in a system without access to high voltage on the A9 pin. The
command sequence is illustrated in "Auto-select Codes".
Byte 0 (A0 = VIL) represents the manufacturer
′s code (Winbond = DAH) and byte 1 (A0 = VIH) the
device identifier code (W39L040 = B6hex). All identifiers for manufacturer and device will exhibit odd
parity with DQ7 defined as the parity bit. In order to read the proper device codes when executing the
Auto-select, A1 must be low state.
6.2 Data Protection
The W39L040 is designed to offer protection against accidental erasure or programming caused by
spurious system level signals that may exist during power transitions. During power up the device
automatically resets the internal state machine in the Read mode. Also, with its control register
architecture, alteration of the memory contents only occurs after successful completion of specific
multi-bus cycle command sequences. The device also incorporates several features to prevent
inadvertent write cycles resulting from VDD power-up and power-down transitions or system noise.
Boot Block Operation
There are four alternatives to set the boot block. Either 16K-byte or 64K-byte in the top/bottom location
of this device can be locked as boot block, which can be used to store boot codes. It is located in the
last 16K/64K bytes or first 16K/64K bytes of the memory with the address range from
7C000/70000(hex) to 7FFFF(hex) for top location or 00000(hex) to 03FFF/0FFFF(hex) for bottom
location.
See Command Codes for Boot Block Lockout Enable for the specific code. Once this feature is set the
data for the designated block cannot be erased or programmed (programming lockout), other memory
locations can be changed by the regular programming method.
In order to detect whether the boot block feature is set on the first/last 16K/64K-bytes block or not,
users can perform software command sequence: enter the product identification mode (see Command
Codes for Identification/Boot Block Lockout Detection for specific code), and then read from address
0002(hex) for first (bottom) location or 7FFF2(hex) for last (top) location. If the DQ0/DQ1 of output
data is "0/1," the 16K-bytes boot block programming lockout feature will be activated; if the DQ0/DQ1
of output data is "1/1," the 64K-bytes boot block programming lockout feature will be activated. If the
DQ0/DQ1 of output data is "0/0," for both 16K/64K-bytes boot block, the lockout feature will be
inactivated and the block can be erased/programmed.
To return to normal operation, perform a three-byte command sequence (or an alternate single-byte
command) to exit the identification mode. For the specific code, see Command Codes for
Identification/Boot Block Lockout Detection.
6.2.1 Low VDD Inhibit
To avoid initiation of a write cycle during VDD power-up and power-down, the W39L040 locks out when
VDD < 2.0V (see DC Characteristics section for voltages). The write and read operations are inhibited
when VDD is less than 2.0V typical. The W39L040 ignores all write and read operations until VDD >
2,0V. The user must ensure that the control pins are in the correct logic state when VDD > 2.0V to
prevent unintentional writes.
6.2.2 Write Pulse "Glitch" Protection
Noise pulses of less than 10 nS (typical) on #OE, #CE, or #WE will not initiate a write cycle.
相关PDF资料 |
PDF描述 |
|---|---|
| P4C1256-20PI | 32K X 8 STANDARD SRAM, 20 ns, PDIP28 |
| P4C1256-25JC | 32K X 8 STANDARD SRAM, 25 ns, PDSO28 |
| P4C1256L-45L32M | 32K X 8 STANDARD SRAM, 45 ns, QCC32 |
| P4C1256L-70CMB | 32K X 8 STANDARD SRAM, 70 ns, CDIP28 |
| P4C169-55LMB | 4K X 4 STANDARD SRAM, 55 ns, CQCC20 |
相关代理商/技术参数 |
参数描述 |
|---|---|
| P4C1256L-70SC | 制造商:未知厂家 制造商全称:未知厂家 功能描述:LOW POWER 32K x 8 STATIC CMOS RAM |
| P4C1256L-70SI | 制造商:未知厂家 制造商全称:未知厂家 功能描述:LOW POWER 32K x 8 STATIC CMOS RAM |
| P4C1256L70SNCLF | 制造商:PYRAMID 制造商全称:Pyramid Semiconductor Corporation 功能描述:LOW POWER 32K x 8 STATIC CMOS RAM |
| P4C1256L70SNILF | 制造商:PYRAMID 制造商全称:Pyramid Semiconductor Corporation 功能描述:LOW POWER 32K x 8 STATIC CMOS RAM |
| P4C1257-20CC | 制造商:未知厂家 制造商全称:未知厂家 功能描述:x1 SRAM |
发布紧急采购，3分钟左右您将得到回复。