参数资料
型号: P4C1281-25DC
厂商: PYRAMID SEMICONDUCTOR CORP
元件分类: SRAM
英文描述: 64K X 4 STANDARD SRAM, 25 ns, CDIP28
封装: 0.300 INCH, CERAMIC, DIP-28
文件页数: 7/11页
文件大小: 862K
代理商: P4C1281-25DC
P4C1281/P4C1282 - ULTRA HIGH SPEED 64K x 4 CMOS STATIC RAMS
Page 5
Document # SRAM136 REV OR
TIMIng WAVEFORM OF WRITE CYCLE nO. 1 (WE COnTROLLED) (10, 11, 12)
Notes:
10. CE and WE must be LOW for WRITE cycle.
11. If CE goes HIGH simultaneously with WE HIGH, the output remains
in a high impedance state
12. Write Cycle Time is measured from the last valid address to the first
transitioning address.
TIMIng WAVEFORM OF WRITE CYCLE nO. 2 (CE COnTROLLED) (10, 11, 12)
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