- 您现在的位置：买卖IC网 > PDF目录367700 > P60ARM-GP1N (Zarlink Semiconductor Inc.) Low power, general purpose 32-bit RISC microprocessor PDF资料下载
参数资料
| 型号： | P60ARM-GP1N |
| 厂商： | Zarlink Semiconductor Inc. |
| 英文描述： | Low power, general purpose 32-bit RISC microprocessor |
| 中文描述： | 低功耗，通用32位RISC微处理器 |
| 文件页数： | 18/120页 |
| 文件大小： | 1275K |
| 代理商： | P60ARM-GP1N |
第1页第2页第3页第4页第5页第6页第7页第8页第9页第10页第11页第12页第13页第14页第15页第16页第17页当前第18页第19页第20页第21页第22页第23页第24页第25页第26页第27页第28页第29页第30页第31页第32页第33页第34页第35页第36页第37页第38页第39页第40页第41页第42页第43页第44页第45页第46页第47页第48页第49页第50页第51页第52页第53页第54页第55页第56页第57页第58页第59页第60页第61页第62页第63页第64页第65页第66页第67页第68页第69页第70页第71页第72页第73页第74页第75页第76页第77页第78页第79页第80页第81页第82页第83页第84页第85页第86页第87页第88页第89页第90页第91页第92页第93页第94页第95页第96页第97页第98页第99页第100页第101页第102页第103页第104页第105页第106页第107页第108页第109页第110页第111页第112页第113页第114页第115页第116页第117页第118页第119页第120页
P60ARM-B
14
To return normally from IRQ, use SUBS PC,R14_irq,#4 which will restore both the PC and the CPSR and
resume execution of the interrupted code. R14_fiq is a symbol for the register R14 and if used needs to be
declared in the users application program.
3.4.3 Abort
An
access cannot be completed. For instance, in a virtual memory system the data corresponding to the current
address may have been moved out of memory onto a disc, and considerable processor activity may be
required to recover the data before the access can be performed successfully. ARM60 checks for ABORT
during memory access cycles. When successfully
aborted ARM60 will respond in one of two ways:
ABORT can be signalled by the external
ABORT
input. ABORT indicates that the current memory
(1)
If the
marked as invalid but the
executed, for example as a result of a branch being taken while it is in the pipeline, no
occur. An
abort will take place if the instruction reaches the head of the pipeline and is about to be
executed.
abort occurred during an instruction prefetch (a
abort exception does not occur immediately. If the instruction is not
Prefetch
Abort
), the prefetched instruction is
abort will
(2)
If the
abort occurred during a data access (a
Dat
a
Abort
), the action depends on the instruction type.
(a) Single data transfer instructions (LDR, STR) are
if the processor is configured for Early
are able to write back modified base registers and the Abort handler must be aware of this.
aborted as though the instruction had not executed
Abort. When configured for Late
Abort, these instructions
(b) The swap instruction (SWP) is
access may take place.
aborted as though it had not executed, though externally the read
(c) Block data transfer instructions (LDM, STM) complete, and if write-back is set, the base is updated.
If the instruction would normally have overwritten the base with data (i.e. LDM with the base in
the transfer list), this overwriting is prevented. All register overwriting is prevented after the
is indicated, which means in particular that R15 (which is always last to be transferred) is preserved
in an aborted LDM instruction.
Abort
When either a prefetch or data abort occurs, ARM60 performs the following:
(1)
Saves the address of the
R14_abt; saves CPSR in SPSR_abt.
aborted instruction plus 4 (for prefetch
aborts) or 8 (for data aborts) in
(2)
Forces M[4:0]=10111 (Abort mode) and sets the I bit in the CPSR.
(3)
Forces the PC to fetch the next instruction from either address 0x0C (prefetch abort) or address 0x10
(data
abort).
To return after fixing the reason for the
PC,R14_abt,#8 (for a data abort). This will restore both the PC and the CPSR and retry the
instruction. R14_fiq is a symbol for the register R14 and if used needs to be declared in the users application
program.
abort, use SUBS PC,R14_abt,#4 (for a prefetch
abort) or SUBS
aborted
The
memory management software is available. The processor is allowed to generate arbitrary addresses, and
when the data at an address is unavailable the MMU signals an
abort mechanism allows a
demand paged virtual memory system
to be implemented when suitable
abort. The processor traps into system
相关PDF资料 |
PDF描述 |
|---|---|
| P60ARM-IG | Low power, general purpose 32-bit RISC microprocessor |
| P60ARM-B | Low power, general purpose 32-bit RISC microprocessor |
| P60A | 60W DC-DC Converter P60A-Series |
| P60A12D05P | 60W DC-DC Converter P60A-Series |
| P60A12D12P | 60W DC-DC Converter P60A-Series |
相关代理商/技术参数 |
参数描述 |
|---|---|
| P60ARM-IG | 制造商:ZARLINK 制造商全称:Zarlink Semiconductor Inc 功能描述:Low power, general purpose 32-bit RISC microprocessor |
| P-60AS/A18 | 功能描述:BATTERY NICAD 2/3A 600MAH W/TAB RoHS:否 类别:电池产品 >> 电池，充电式（蓄电池） 系列:- MSDS 材料安全数据表:Nickel Metal Hydride Battery MSDS 标准包装:1,000 系列:TWICELL 电池化学:镍金属氢化物 电池大小:AAA 电压 - 额定:1.2V 容量:930mAh 尺寸/尺寸:- 端接类型:焊片 放电速率:186mA 标准充电电流:100mA 标准充电时间:16小时 重量:0.029 磅（13.15g） 装运信息:- 其它名称:SY153T |
| P60AS302 | 制造商:APEM 功能描述: |
| P60AS632-8C | 制造商:NYLOK 功能描述: |
| P60AS701 | 功能描述:旋钮开关 10POS BCD 0.15A 24V RoHS:否 制造商:C&K Components 位置数量:5 卡片组数量: 每卡片组极数:2 电流额定值:250 mA 电压额定值:125 V 指数角: 触点类型: 触点形式:DPST 端接类型:Solder 安装类型:Panel 触点电镀:Silver |
发布紧急采购，3分钟左右您将得到回复。