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参数资料
| 型号： | P80C152JD |
| 厂商： | Intel Corp. |
| 英文描述： | UNIVERSAL COMMUNICATION CONTROLLER 8-BIT MICROCONTROLLER |
| 中文描述： | 全球通信控制器8位微控制器 |
| 文件页数： | 7/17页 |
| 文件大小： | 233K |
| 代理商： | P80C152JD |
8XC152JA/JB/JC/JD
OSCILLATOR CHARACTERISTICS
XTAL1 and XTAL2 are the input and output, respec-
tively, of an inverting amplifier which can be config-
ured for use as an on-chip oscillator, as shown in
Figure 3.
To drive the device from an external clock source,
XTAL1 should be driven, while XTAL2 is left uncon-
nected, as shown in Figure 4. There are no require-
ments on the duty cycle of the external clock signal,
since the input to the internal clocking circuitry is
through a divide-by-two flip-flop, but minimum and
maximum high and low times specified on the Data
Sheet must be observed.
An external oscillator may encounter as much as a
100 pF load at XTAL1 when it starts-up. This is due
to interaction between the amplifier and its feedback
capacitance. Once the external signal meets the V
IL
and V
IH
specifications the capacitance will not ex-
ceed 20 pF.
270431–5
Figure 3. Using the On-Chip Oscillator
270431–6
Figure 4. External Clock Drive
IDLE MODE
In Idle Mode, the CPU puts itself to sleep while most
of the on-chip peripherals remain active. The major
peripherals that do not remain active during Idle, are
the DMA channels. The Idle Mode is invoked by
software. The content of the on-chip RAM and all
the Special Function Registers remain unchanged
during this mode. The Idle Mode can be terminated
by any enabled interrupt or by a hardware reset.
POWER DOWN MODE
In Power Down Mode, the oscillator is stopped and
all on-chip functions cease except that the on-chip
RAM contents are maintained. The mode Power
Down is invoked by software. The Power Down
Mode can be terminated only by a hardware reset.
Table 3. Status of the External Pins During Idle and Power Down Modes
80C152JA/83C152JA/80C152JC/83C152JC
Mode
Program
Memory
ALE
PSEN
Port 0
Port 1
Port 2
Port 3
Port 4
Idle
Internal
1
1
Data
Data
Data
Data
Data
Idle
External
1
1
Float
Data
Address
Data
Data
Power Down
Internal
0
0
Data
Data
Data
Data
Data
Power Down
External
0
0
2
Float
Data
Data
Data
Data
80C152JB/80C152JD
Mode
Instruction
Bus
ALE PSEN EPSEN Port 0 Port 1
Port 2
Port 3 Port 4 Port 5
Port 6
Idle
P0, P2
1
1
1
Float
Data
Address
Data
Data
0FFH
0FFH
Idle
P5, P6
1
1
1
Data
Data
Data
Data
Data
0FFH Address
Power Down
P0, P2
0
0
1
Float
Data
Data
Data
Data
0FFH
0FFH
Power Down
P5, P6
0
1
2
0
Data
Data
Data
Data
Data
0FFH
0FFH
NOTE:
For more detailed information on the reduced power modes refer to the Embedded Controller Handbook, and Application
Note AP-252, ‘‘Designing with the 80C51BH.’’
2
Note difference of logic level of PSEN during Power Down for ROM JA/JC and ROM emulation mode for JC/JD.
7
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