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参数资料
| 型号： | P80C31X2BN,112 |
| 厂商： | NXP Semiconductors |
| 文件页数： | 25/62页 |
| 文件大小： | 0K |
| 描述： | IC 80C51 MCU 128 ROMLESS 40DIP |
| 标准包装： | 9 |
| 系列： | 80C |
| 核心处理器： | 8051 |
| 芯体尺寸： | 8-位 |
| 速度： | 33MHz |
| 连通性： | EBI/EMI，UART/USART |
| 外围设备： | POR |
| 输入/输出数： | 32 |
| 程序存储器类型： | ROMless |
| RAM 容量： | 128 x 8 |
| 电压 - 电源 (Vcc/Vdd)： | 2.7 V ~ 5.5 V |
| 振荡器型： | 内部 |
| 工作温度： | 0°C ~ 70°C |
| 封装/外壳： | 40-DIP（0.600"，15.24mm） |
| 包装： | 管件 |
| 其它名称： | 935269613112 P80C31X2BN P80C31X2BN-ND |
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Philips Semiconductors
Product data
P80C3xX2; P80C5xX2;
P87C5xX2
80C51 8-bit microcontroller family
4K/8K/16K/32K ROM/OTP, low voltage (2.7 to 5.5 V),
low power, high speed (30/33 MHz)
2003 Jan 24
31
SCON Address = 98H
Reset Value = 0000 0000B
SM0/FE
SM1
SM2
REN
TB8
RB8
Tl
Rl
Bit Addressable
(SMOD0 = 0/1)*
Symbol
Position
Function
FE
SCON.7
Framing Error bit. This bit is set by the receiver when an invalid stop bit is detected. The FE bit is not
cleared by valid frames but should be cleared by software. The SMOD0 bit must be set to enable
access to the FE bit.*
SM0
SCON.7
Serial Port Mode Bit 0, (SMOD0 must = 0 to access bit SM0)
SM1
SCON.6
Serial Port Mode Bit 1
SM2
SCON.5
Enables the Automatic Address Recognition feature in Modes 2 or 3. If SM2 = 1 then Rl will not be set
unless the received 9th data bit (RB8) is 1, indicating an address, and the received byte is a Given or
Broadcast Address. In Mode 1, if SM2 = 1 then Rl will not be activated unless a valid stop bit was
received, and the received byte is a Given or Broadcast Address. In Mode 0, SM2 should be 0.
REN
SCON.4
Enables serial reception. Set by software to enable reception. Clear by software to disable reception.
TB8
SCON.3
The 9th data bit that will be transmitted in Modes 2 and 3. Set or clear by software as desired.
RB8
SCON.2
In modes 2 and 3, the 9th data bit that was received. In Mode 1, if SM2 = 0, RB8 is the stop bit that
was received.
In Mode 0, RB8 is not used.
Tl
SCON.1
Transmit interrupt flag. Set by hardware at the end of the 8th bit time in Mode 0, or at the beginning of
the stop bit in the other modes, in any serial transmission. Must be cleared by software.
Rl
SCON.0
Receive interrupt flag. Set by hardware at the end of the 8th bit time in Mode 0, or halfway through the
stop bit time in the other modes, in any serial reception (except see SM2). Must be cleared by
software.
NOTES:
*SMOD0 is located at PCON.6.
**fOSC = oscillator frequency
SU01628
7654
321
0
SM0
SM1
Mode
Description
Baud Rate**
0
shift register
fOSC/12 (12-clk mode) or fOSC/6 (6-clk mode)
0
1
8-bit UART
variable
1
0
2
9-bit UART
fOSC/64 or fOSC/32 or fOSC/16 (6-clock mode) or
fOSC/32 (12-clock mode)
1
3
9-bit UART
variable
Figure 18. SCON: Serial Port Control Register
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相关代理商/技术参数 |
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|---|---|
| P80C32 | 制造商:TEMIC 制造商全称:TEMIC Semiconductors 功能描述:CMOS 0 to 44 MHz Single Chip 8?bit Microntroller |
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