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参数资料
| 型号： | P80C32SBBB,557 |
| 厂商： | NXP Semiconductors |
| 文件页数： | 9/32页 |
| 文件大小： | 0K |
| 描述： | IC 80C51 MCU 256 ROMLESS 44-QFP |
| 产品培训模块： | Migrating from 8/16-Bit MCUs to 32-Bit ARMs |
| 标准包装： | 480 |
| 系列： | 80C |
| 核心处理器： | 8051 |
| 芯体尺寸： | 8-位 |
| 速度： | 16MHz |
| 连通性： | UART/USART |
| 外围设备： | POR |
| 输入/输出数： | 32 |
| 程序存储器类型： | ROMless |
| RAM 容量： | 256 x 8 |
| 电压 - 电源 (Vcc/Vdd)： | 2.7 V ~ 5.5 V |
| 振荡器型： | 内部 |
| 工作温度： | 0°C ~ 70°C |
| 封装/外壳： | 44-QFP |
| 包装： | 托盘 |
| 其它名称： | 935255820557 P80C32SBBB P80C32SBBB-ND |
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Philips Semiconductors
Product specification
80C31/80C32
80C51 8-bit microcontroller family
128/256 byte RAM ROMless low voltage (2.7V–5.5V),
low power, high speed (33 MHz)
2000 Aug 07
17
Interrupt Priority Structure
The 80C31 and 80C32 have a 6-source four-level interrupt
structure. They are the IE, IP and IPH. (See Figures 10, 11, and 12.)
The IPH (Interrupt Priority High) register that makes the four-level
interrupt structure possible. The IPH is located at SFR address B7H.
The structure of the IPH register and a description of its bits is
shown in Figure 12.
The function of the IPH SFR is simple and when combined with the
IP SFR determines the priority of each interrupt. The priority of each
interrupt is determined as shown in the following table:
PRIORITY BITS
INTERRUPT PRIORITY LEVEL
IPH.x
IP.x
INTERRUPT PRIORITY LEVEL
0
Level 0 (lowest priority)
0
1
Level 1
1
0
Level 2
1
Level 3 (highest priority)
An interrupt will be serviced as long as an interrupt of equal or
higher priority is not already being serviced. If an interrupt of equal
or higher level priority is being serviced, the new interrupt will wait
until it is finished before being serviced. If a lower priority level
interrupt is being serviced, it will be stopped and the new interrupt
serviced. When the new interrupt is finished, the lower priority level
interrupt that was stopped will be completed.
Table 7.
Interrupt Table
SOURCE
POLLING PRIORITY
REQUEST BITS
HARDWARE CLEAR?
VECTOR ADDRESS
X0
1
IE0
N (L)1
Y (T)2
03H
T0
2
TP0
Y
0BH
X1
3
IE1
N (L)
Y (T)
13H
T1
4
TF1
Y
1BH
SP
5
RI, TI
N
23H
T2
6
TF2, EXF2
N
2BH
NOTES:
1. L = Level activated
2. T = Transition activated
EX0
IE (0A8H)
Enable Bit = 1 enables the interrupt.
Enable Bit = 0 disables it.
BIT
SYMBOL
FUNCTION
IE.7
EA
Global disable bit. If EA = 0, all interrupts are disabled. If EA = 1, each interrupt can be individually
enabled or disabled by setting or clearing its enable bit.
IE.6
—
Not implemented. Reserved for future use.
IE.5
ET2
Timer 2 interrupt enable bit.
IE.4
ES
Serial Port interrupt enable bit.
IE.3
ET1
Timer 1 interrupt enable bit.
IE.2
EX1
External interrupt 1 enable bit.
IE.1
ET0
Timer 0 interrupt enable bit.
IE.0
EX0
External interrupt 0 enable bit.
SU00571
ET0
EX1
ET1
ES
ET2
—
EA
0
1
2
3
4
5
6
7
Figure 10. IE Registers
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| P80C32SBBB-S | 制造商:未知厂家 制造商全称:未知厂家 功能描述:8-Bit Microcontroller |
| P80C32SBPN | 制造商:NXP Semiconductors 功能描述:80C 16MHz 制造商:NXP Semiconductors 功能描述:IC 8BIT CPU 80C32 DIP40 制造商:NXP Semiconductors 功能描述:IC, 8BIT CPU, 80C32, DIP40 制造商:NXP Semiconductors 功能描述:IC, 8BIT MCU, 80C51, 16MHZ, DIP-40; Controller Family/Series:(8051) 8052; Core Size:8bit; No. of I/O's:32; Supply Voltage Min:2.7V; Supply Voltage Max:5.5V; Digital IC Case Style:DIP; No. of Pins:40; Program Memory Size:- ;RoHS Compliant: Yes |
| P80C32SBPN,112 | 功能描述:8位微控制器 -MCU 80C51 256B 16MHZ ROMLESS RoHS:否 制造商:Silicon Labs 核心:8051 处理器系列:C8051F39x 数据总线宽度:8 bit 最大时钟频率:50 MHz 程序存储器大小:16 KB 数据 RAM 大小:1 KB 片上 ADC:Yes 工作电源电压:1.8 V to 3.6 V 工作温度范围:- 40 C to + 105 C 封装 / 箱体:QFN-20 安装风格:SMD/SMT |
| P80C32SBPN112 | 制造商:NXP Semiconductors 功能描述:IC 8BIT MCU 80C51 16MHZ DIP-40 |
| P80C32SFAA | 制造商:PHILIPS 制造商全称:NXP Semiconductors 功能描述:8-bit CMOS (low voltage, low power and high speed) microcontroller families |
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