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参数资料
| 型号： | P80C32SBPN,112 |
| 厂商： | NXP Semiconductors |
| 文件页数： | 11/32页 |
| 文件大小： | 0K |
| 描述： | IC 80C51 MCU 256X8 ROMLESS 40DIP |
| 产品培训模块： | Migrating from 8/16-Bit MCUs to 32-Bit ARMs |
| 标准包装： | 9 |
| 系列： | 80C |
| 核心处理器： | 8051 |
| 芯体尺寸： | 8-位 |
| 速度： | 16MHz |
| 连通性： | UART/USART |
| 外围设备： | POR |
| 输入/输出数： | 32 |
| 程序存储器类型： | ROMless |
| RAM 容量： | 256 x 8 |
| 电压 - 电源 (Vcc/Vdd)： | 2.7 V ~ 5.5 V |
| 振荡器型： | 内部 |
| 工作温度： | 0°C ~ 70°C |
| 封装/外壳： | 40-DIP（0.600"，15.24mm） |
| 包装： | 管件 |
| 产品目录页面： | 705 (CN2011-ZH PDF) |
| 其它名称： | 568-1005-5 935255880112 P80C32SBPN |
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Philips Semiconductors
Product specification
80C31/80C32
80C51 8-bit microcontroller family
128/256 byte RAM ROMless low voltage (2.7V–5.5V),
low power, high speed (33 MHz)
2000 Aug 07
19
Reduced EMI Mode
The AO bit (AUXR.0) in the AUXR register when set disables the
ALE output.
Reduced EMI Mode
AUXR (8EH)
7
6
54
32
1
0
–
AO
AUXR.0
AO
Turns off ALE output.
Dual DPTR
The dual DPTR structure (see Figure 13) enables a way to specify
the address of an external data memory location. There are two
16-bit DPTR registers that address the external memory, and a
single bit called DPS = AUXR1/bit0 that allows the program code to
switch between them.
New Register Name: AUXR1#
SFR Address: A2H
Reset Value: xxx000x0B
AUXR1 (A2H)
76
54
32
10
–
WUPD
0
–
DPS
Where:
DPS = AUXR1/bit0 = Switches between DPTR0 and DPTR1.
Select Reg
DPS
DPTR0
0
DPTR1
1
The DPS bit status should be saved by software when switching
between DPTR0 and DPTR1.
Note that bit 2 is not writable and is always read as a zero. This
allows the DPS bit to be quickly toggled simply by executing an INC
DPTR instruction without affecting the WOPD or LPEP bits.
DPS
DPTR1
DPTR0
DPH
(83H)
DPL
(82H)
EXTERNAL
DATA
MEMORY
SU00745A
BIT0
AUXR1
Figure 13.
DPTR Instructions
The instructions that refer to DPTR refer to the data pointer that is
currently selected using the AUXR1/bit 0 register. The six
instructions that use the DPTR are as follows:
INC DPTR
Increments the data pointer by 1
MOV DPTR, #data16
Loads the DPTR with a 16-bit constant
MOV A, @ A+DPTR
Move code byte relative to DPTR to ACC
MOVX A, @ DPTR
Move external RAM (16-bit address) to
ACC
MOVX @ DPTR , A
Move ACC to external RAM (16-bit
address)
JMP @ A + DPTR
Jump indirect relative to DPTR
The data pointer can be accessed on a byte-by-byte basis by
specifying the low or high byte in an instruction which accesses the
SFRs. See application note AN458 for more details.
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