参数资料
型号: P80C528FFB
厂商: NXP SEMICONDUCTORS
元件分类: 微控制器/微处理器
英文描述: CMOS single-chip 8-bit microcontroller
中文描述: 8-BIT, 16 MHz, MICROCONTROLLER, PQFP44
文件页数: 13/26页
文件大小: 447K
代理商: P80C528FFB
Philips Semiconductors
Product specification
80C528/83C528
CMOS single-chip 8-bit microcontrollers
1995 Feb 02
13
DC ELECTRICAL CHARACTERISTICS
(Continued)
T
amb
= 0
°
C to +70
°
C (V
DD
= 5V
±
20%), –40
°
C to +85
°
C (V
DD
= 5V
±
20%), or –40
°
C to +125
°
C (V
DD
= 5V
±
10%), V
SS
=0V
TEST
LIMITS
SYMBOL
PARAMETER
PART TYPE
CONDITIONS
MIN
MAX
UNIT
I
IL1
Input leakage current, port 0, EA
0.45<Vi<V
DD
±
10
μ
A
I
IL2
Input leakage current, P1.6/SCL, P1.7/SDA
0V<Vi<6.0V
0V<V
DD
<6.0V
See notes 6, 7
±
10
μ
A
μ
A
I
DD
Power supply current:
Active mode
Idle mode
Power down mode
Power down mode
Internal reset pull-down resistor
Capacitance of I/O buffer
35
6
100
150
150
10
mA
mA
μ
A
μ
A
k
pF
–40
°
C to +125
°
C
R
RST
C
IO
50
Freq.=1MHz
T
amb
= 25
°
C
NOTES:
1. Capacitive loading on Port 0 and Port 2 may cause spurious noise pulses to be superimposed on the LOW level ouput voltage of ALE, Port
1 and Port 3. The noise is due to external bus capacitance discharging into the Port 0 and Port 2 pins when these pins make a 1-to-0
transition during bus operations. In the worst cases (capacitive loading > 100pF), the noise pulse on the ALE line may exceed 0.8V. In such
cases it may be desirable to qualify ALE with a Schmitt Trigger, or use an address latch with a Schmitt Trigger STROBE input.
2. Capacitive loading on Port 0 and Port 2 may cause the HIGH level output voltage on ALE and PSEN to momentarily fall below the 0.9V
DD
specification when the address bits are stabilizing.
3. The input threshold voltage of P1.6 and P1.7 (SIO1) meets the I
2
C specification, so a voltage below 0.3V
DD
will be recognized as a logic 0
while an input above 0.7V
will be recognized as a logic 1.
4. Under steady state (non-transient) conditions, I
OL
must be externally limited as follows:
Maximum I
OL
per port pin:
10mA
Maximum I
OL
per 8–bit port: –
Port 0:
26mA
Ports 1, 2, & 3:
15mA
Maximum total I
OL
for all output pins:
71mA
If I
OL
exceeds the test condition, V
OL
may exceed the related specification. Pins are not guaranteed to sink current greater than the listed
test conditions.
5. Pins of ports 1, 2, and 3 source a transition current when they are being externally driven from 1 to 0. The transition current reaches its
maximum value when V
IN
is approximately 2V.
6. See Figures 9 through 12 for I
DD
test conditions.
7. I
DDMAX
at other frequencies can be derived from the figure below, where FREQ is the external oscillator frequency in MHz.
I
DDMAX
is given in mA.
35
30
25
20
15
10
5
0
MAX ACTIVE MODE
TYP ACTIVE MODE
MAX IDLE MODE
TYP IDLE MODE
I
I
DD
vs. FREQUENCY
D
FREQ. AT XTAL1 (MHz)
4
8
12
16
VALID ONLY WITHIN FREQUENCY SPECIFICATIONS OF DEVICE UNDER TEST.
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