参数资料
型号: P83C152JB
厂商: Intel Corp.
英文描述: UNIVERSAL COMMUNICATION CONTROLLER 8-BIT MICROCONTROLLER
中文描述: 全球通信控制器8位微控制器
文件页数: 4/17页
文件大小: 233K
代理商: P83C152JB
8XC152JA/JB/JC/JD
80C152JB/JD General Description
The 80C152JB/JD is a ROMless extension of the
80C152 Universal Communication controller. The
80C152JB has the same five 8-bit I/O ports of the
80C152, plus an additional two 8-bit I/O ports, Port 5
and Port 6. The 80C152JB/JD also has two addi-
tional control pins, EBEN (
E
PROM
B
us
EN
able), and
EPSEN (
E
PROM bus
P
rogram
S
tore
EN
able).
EBEN selects the functionality of Port 5 and Port 6.
When EBEN is low, these ports are strictly I/O, simi-
lar to Port 4. The SFR location for Port 5 is 91H and
Port 6 is 0A1H. This means Port 5 and Port 6 are not
bit addressable. With EBEN low, all program memo-
ry fetches take place via Port 0 and Port 2. (The
80C152 is a ROMless only product). When EBEN is
high, Port 5 and Port 6 form an address/data bus
called the E-Bus (EPROM-Bus) for program memory
operations.
EPSEN is used in conjunction with Port 5 and Port 6
program memory operations. EPSEN functions like
PSEN during program memory operation, but sup-
ports Port 5 and Port 6. EPSEN is the read strobe to
external program memory for Port 5 and Port 6.
EPSEN is activated twice during each machine cycle
unless an external data memory operation occurs on
Port(s) 0 and Port 2. When external data memory is
accessed the second activation of EPSEN is
skipped, which is the same as when using PSEN.
Note that data memory fetches cannot be made
through Ports 5 and 6.
When EBEN is high and EA is low, all program mem-
ory operations take place via Ports 5 and 6. The high
byte of the address goes out on Port 6, and the low
byte is output on Port 5. ALE is still used to latch the
address on Port 5. Next, the op code is read on Port
5. The timing is the same as when using Ports 0 and
2 for external program memory operations.
Table 1. Program Memory Fetches
EBEN
EA
Program
Fetch via
PSEN
EPSEN
Comments
0
0
P0, P2
Active
Inactive
Addresses 0–0FFFFH
0
1
N/A
N/A
N/A
Invalid Combination
1
0
P5, P6
Inactive
Active
Addresses 0–0FFFFH
1
1
P5, P6
P0, P2
Inactive
Active
Active
Inactive
Addresses 0–1FFFH
Addresses
t
2000H
Table 2. 8XC152 Product Differences
ROMless
Version
CSMA/CD
and
HDLC/SDLC
*
*
HDLC/SDLC
Only
ROM
Version
Available
*
(83C152JA)
PLCC
and
DIP
*
PLCC
Only
5 I/O
Ports
7 I/0
Ports
80C152JA
*
80C152JB
*
*
80C152JC
*
*
*
(83C152JC)
*
*
80C152JD
*
*
NOTES:
*
e
options available
0 standard frequency range 3.5 MHz to 12 MHz
0 ‘‘
b
1’’ frequency range 3.5 MHz to 16.5 MHz
4
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