
8xC251TB/TQ HIGH-PERFORMANCE CHMOS MICROCONTROLLER
13
VOH1
Output High Voltage
(Port 0 in External
Address)
VCC – 0.3
VCC – 0.7
VCC – 1.5
V
IOH = -200 A
IOH = -3.2 mA
IOH = -7.0 mA
VOH2
Output High Voltage
(Port 2 in External
Address during Page
Mode)
VCC – 0.3
VCC – 0.7
VCC – 1.5
V
IOH = -200 A
IOH = -3.2 mA
IOH = -7.0 mA
IIL
Logical 0 Input
Current (Port 1, 2, 3)
-50
A
VIN = 0.45 V
ILI
Input Leakage
Current (Port 0)
+/-10
A
0.45 < VIN < VCC
ITL
Logical 1-to-0
Transition Current
(Port 1, 2, 3)
-650
A
VIN = 2.0 V
RRST
RST Pulldown
Resistor
40
225
k
CIO
Pin Capacitance
10
(Note 4)
pF
FOSC = 24 MHz
TA = 25 °C
IPD
Powerdown Current
10
(Note 4)
20
A
IDL
Idle Mode Current
35
(Note 4)
44
mA
F
OSC = 24 MHz
ICC
Operating Current
70
(Note 4)
83
mA
F
OSC = 24 MHz
NOTES:
1. Under steady-state (non-transient) conditions, IOL must be externally limited as follows:
Maximum IOL per port pin:10 mA
Maximum IOL per 8-bit port:
port 0
26 mA
ports 1–3
15 mA
Maximum Total IOL for
all output pins
71 mA
If IOL exceeds the test conditions, VOL may exceed the related specification. Pins are not guaranteed to sink current
greater than the listed test conditions.
2. Capacitive loading on ports 0 and 2 may cause spurious noise pulses above 0.4 V on the low-level outputs of ALE and
ports 1, 2, and 3. The noise is due to external bus capacitance discharging into the port 0 and port 2 pins when these pins
change from high to low. In applications where capacitive loading exceeds 100 pF, the noise pulses on these signals may
exceed 0.8 V. It may be desirable to qualify ALE or other signals with a Schmitt trigger or CMOS-level input logic.
3. Capacitive loading on ports 0 and 2 causes the VOH on ALE and PSEN# to drop below the specification when the address
lines are stabilizing.
Typical values are obtained using VCC = 5.0, TA = 25°C and are not guaranteed.
Table 9. DC Characteristics at VCC = 4.5 – 5.5 V (Sheet 2 of 2)
Symbol
Parameter
Min
Typical
Max
Units
Test Conditions