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参数资料
| 型号： | P83C266BDR |
| 厂商： | NXP SEMICONDUCTORS |
| 元件分类： | 微控制器/微处理器 |
| 英文描述： | Microcontrollers for PAL/SECAM TV with OSD and VST |
| 中文描述： | 8-BIT, MROM, 12 MHz, MICROCONTROLLER, PDIP42 |
| 封装： | 0.600 INCH, PLASTIC, SDIP-42 |
| 文件页数： | 15/92页 |
| 文件大小： | 382K |
| 代理商： | P83C266BDR |
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1999 Mar 10
15
Philips Semiconductors
Product specification
Microcontrollers for PAL/SECAM TV
with OSD and VST
P8xCx66 family
9
REDUCED POWER MODE
Only one reduced power mode is implemented; this is the
Idle mode.
During Idle mode all blocks are inactive except Timer 0,
Timer 1, INT0, INT1 and the Watchdog timer. These active
functions may generate an interrupt (if their interrupts are
enabled) and this will cause the device to leave the Idle
mode.
The Idle mode is activated by software using the PCON
register; this register is described in Section 9.6.
9.1
Idle mode
The instruction that sets PCON.0 is the last instruction
executed before entering the Idle mode. Once in the Idle
mode, the internal clock is gated away from the CPU and
from all derivative functions (PWM/TPWM/ADC/I
2
C-bus),
except Timer 0, Timer 1 and interrupts INT0 and INT1.
The Watchdog timer remains active. The CPU status is
preserved along with the Stack Pointer, Program Counter,
Program Status Word and the Accumulator. The RAM and
all other registers maintain their data during Idle mode and
the port pins retain the logic states held at Idle mode
activation. The OSD clock is gated away from OSD circuit
in Idle mode.
9.2
Recover from Idle mode
There are 3 methods used to terminate the Idle mode.
9.2.1
V
IA AN
I
NTERRUPT
Activation of INT0, INT1 or an interrupt from Timer 0 or
Timer 1 will cause PCON to be cleared by hardware thus
terminating the Idle mode. The interrupt is serviced and
following the RETI instruction, the next instruction to be
executed will be the one following the instruction that put
the device in the Idle mode. All the other interrupts are
disabled and will not generate an interrupt to wake-up the
CPU.
9.2.2
V
IA
R
ESET
The second method of terminating the Idle mode is with an
external hardware reset. Since the oscillator is still
running, the hardware reset is required to be active for only
two machine cycles to complete the reset operation. Reset
redefines all SFRs, but does not effect the on-chip RAM.
9.2.3
V
IA A
W
ATCHDOG TIMER OVERFLOW
If the Watchdog timer is allowed to overflow or an
erroneous processor state causes an overflow, a
hardware reset will be generated, thus terminating the Idle
mode.
9.3
General purpose flags (GF0 and GF1)
Flags GF0 and GF1 may be used to determine whether
the interrupt was received during normal execution or Idle
mode. For example, the instruction that writes to PCON.0
to set the Idle mode can also set or clear one or both flags.
When the Idle mode is terminated by an interrupt, the
service routine can examine the status of the flag bits.
9.4
Output in Idle mode
Ports will keep the value they had before entering the
Idle mode
The PWM0 to PWM7 outputs will be LOW
The TPWM output will be LOW
The I
2
C-bus output is HIGH
The pins R, G, B and FB will be the ‘inverse of Bp’,
(defined by bit 2 of SFR OSCON).
9.5
Pending interrupts in Idle mode
If pending interrupts (I
2
C-bus, VSYNC, P1.0 to P1.4 or
P1.7) are present at the moment the CPU is switched to
Idle mode, then these interrupts will wake-up the CPU.
If this is not wanted then before entering the Idle mode all
interrupts must be disabled, except those interrupts
allowed to wake-up the CPU (INT0, INT1, Timer 0 and
Timer1). New interrupts from I
2
C-bus, VSYNC,
P1.0 to P1.4 or P1.7 are disabled as soon as Idle mode is
entered.
For example if a high priority interrupt is serviced just
before the instruction which sets PCON.0 and a lower
priority interrupt is generated during the interrupt service
routine of the high priority interrupt, then the lower priority
interrupt is pending. After the high priority interrupt is
serviced (last instruction of routine is RETI) the main
program will execute at least one more instruction to
prevent a deadlock of the main program. In this case, it is
the instruction which sets the PCON.0 bit (enter Idle
mode). The pending lower level interrupt will, if enabled,
immediately wake-up the CPU for an interrupt service,
even though this interrupt is not INT0, INT1 or an interrupt
from Timer 1 or Timer 0.
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| P83C270 | 制造商:PHILIPS 制造商全称:NXP Semiconductors 功能描述:Microcontrollers for NTSC TVs with On-Screen Display OSD and Closed Caption CC |
| P83C270AAR | 制造商:PHILIPS 制造商全称:NXP Semiconductors 功能描述:Microcontrollers for NTSC TVs with On-Screen Display OSD and Closed Caption CC |
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| P83C366BDA | 制造商:PHILIPS 制造商全称:NXP Semiconductors 功能描述:Microcontrollers for PAL/SECAM TV with OSD and VST |
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