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参数资料
| 型号： | P83C366CBP |
| 厂商： | NXP SEMICONDUCTORS |
| 元件分类： | 微控制器/微处理器 |
| 英文描述： | Microcontrollers for PAL/SECAM TV with OSD and VST(带 OSD和 VST的在PAL/SECAM TV中应用的微控制器) |
| 中文描述： | 8-BIT, MROM, 12 MHz, MICROCONTROLLER, PDIP42 |
| 封装： | 0.600 INCH, PLASTIC, SDIP-42 |
| 文件页数： | 38/92页 |
| 文件大小： | 382K |
| 代理商： | P83C366CBP |
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1999 Mar 10
38
Philips Semiconductors
Product specification
Microcontrollers for PAL/SECAM TV
with OSD and VST
P8xCx66 family
15.2
14-bit PWM output (TPWM)
The on-chip 14-bit DAC has one output with a resolution of
16384 levels for Voltage Synthesized Tuning (VST).
The output is active HIGH, the HIGH period being
determined by the values stored in the SFRs TDACH and
TDACL. The 14-bit DAC output is connected to the TPWM
pin.
TPWM shares the same pin as port line P5.0. Selection of
the pin function as either a PWM output or as a port line is
achieved using the TPWME bit in SFR TDACH, see
Section 15.2.5.
The block diagram for the 14-bit PWM circuit is shown in
Fig.22 and consists of:
Two 7-bit SFRs: TDACH and TDACL
One 14-bit register TDACREG
One coarse control block for the generation of the
coarse adjustment pulse
One fine control block for the generation of the fine
adjustment pulses
One 14-bit counter running at f
TDAC
One mixer block that combines the coarse adjustment
pulse and fine tuning pulses; the resultant pulse pattern
is fed to the TPWM output.
Data is loaded into the 14-bit data latch (TDACREG) from
the two 7-bit data latches (TDACL and TDACH) at the
beginning of the first T
sub
period, after TDACH has been
written to. To ensure that correct data is loaded into
TDACREG, the data held in TDACL must be valid before
the write operation to TDACH is started. In other words,
TDACL must be written first before TDACH can be written
to. Examples of valid and invalid loading sequences are
shown in Fig.23.
Once TDACREG has been loaded it takes one T
sub
period
to generate the appropriate pulse patterns. To ensure
correct operation of the DAC, two T
sub
periods should be
allowed before any further changes to the data latches are
made.
The upper seven bits of TDACREG, identified as VSTH,
are used for coarse adjustment and the lower seven bits,
identified as VSTL, are used for fine adjustment.
The outputs OUT1 and OUT2 of the coarse and fine pulse
controllers are ‘ORed’ in the mixer to give the TPWM
output.
The 14-bit counter is continuously running and is clocked
by f
TDAC
which is
1
4
f
osc
.
Figure 24 shows the output of the coarse pulse controller
when VSTH = 001 1101; Fig.25 shows the output of the
fine pulse controller when VSTL = 1111010, and Fig.26
shows a typical TPWM output after the ‘OR’ operation has
been carried out by the mixer.
15.2.1
R
EPETITION TIME OF
OUT1
AND
OUT2:
The repetition period of OUT1 (T
sub
) may be calculated as
shown in Equation (1).
f
TDAC
(1)
Where
The repetition period of OUT2 (T
std
) may be calculated as
shown in Equation (2).
f
TDAC
(2)
15.2.2
C
OARSE ADJUSTMENT
An active HIGH pulse is generated in every subperiod
(except the first one); the pulse duration being determined
by the contents of VSTH. The coarse pulses are generated
at the OUT1 output. The coarse pulse output is LOW at the
start of each subperiod and will remain LOW until the time
has elapsed. The output will then go
HIGH and remain HIGH until the start of the next
subperiod. The coarse pulse duration is
The trailing edge of each coarse pulse coincides with the
end of each T
sub
period. If VSTH = 0000000, then the
coarse output is LOW for the complete period. If the
contents of VSTH = 1111111, then the coarse output is
LOW for the first t
0
period but will go HIGH for the
remaining 127
×
t
0
periods of Tsub.
.
15.2.3
F
INE ADJUSTMENT
Fine adjustment is achieved by generating an additional
pulse in specific subperiods. These additional pulses
appear at the OUT2 output. The pulse is added at the start
of the selected subperiod and has a pulse width of t
0
.
The value held in VSTL determines the subperiod in which
an additional pulse is generated and also determines the
number of additional pulses that will be added during one
T
std
period. Table 39 shows the relationship between the
value held in VSTL, the subperiod during which an
additional pulse OUT2 is generated and the total number
of additional OUT2 pulses generated.
T
sub
--128
128
t
0
×
=
=
t
0
f
TDAC
----1
=
T
std
-128
128
×
16384
t
0
×
=
=
128
VSTH
–
(
)
t
0
×
[
]
VSTH
t
0
×
(
)
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