参数资料
型号: P83C380
厂商: NXP SEMICONDUCTORS
元件分类: 微控制器/微处理器
英文描述: Microcontrollers for monitors with DDC interface, auto-sync detection and sync proc(带DDC接口,同步监测和同步处理的监视器微控制器)
中文描述: 8-BIT, MROM, 16 MHz, MICROCONTROLLER, PDIP42
封装: 0.600 INCH, PLASTIC, SOT-270-1, SDIP-42
文件页数: 21/84页
文件大小: 420K
代理商: P83C380
1997 Dec 12
21
Philips Semiconductors
Product specification
Microcontrollers for monitors with DDC
interface, auto-sync detection and sync proc.
P83Cx80; P87C380
9
WATCHDOG TIMER
In addition to the standard timers, a Watchdog Timer
consisting of an 10-bit prescaler and an 8-bit timer is also
incorporated. The timer is increased every 19.5 ms for an
oscillator frequency of 16 MHz; this is derived from the
oscillator frequency (f
clk
) by the formula:
f
304
1024
×
When a timer overflow occurs, the microcontroller is reset.
To prevent a system reset, the timer must be reloaded
before an overflows occurs, by the application software.
If the processor suffers a hardware/software malfunction,
the software will fail to reload the timer. This failure will
produce a reset upon overflow thus preventing the
processor running out of control.
The Watchdog Timer can only be reloaded if the condition
flag WLE (PCON.4) has been previously set by software.
At the moment the counter is loaded the condition flag is
automatically cleared.
In the Idle mode the Watchdog Timer and reset circuitry
remain active.
The time interval between timer reloading and the
occurrence of a reset, depends on the reloaded value.
f
timer
-----------------------------
=
The Watchdog Timer’s time interval is:
T2
)
Where T2 = decimal value of the T2 register contents and
t
1
= 15.2
μ
s (f
clk
= 10 MHz); t
1
= 12.7
μ
s (f
clk
= 12 MHz)
and t
1
= 19
μ
s (f
clk
= 16 MHz).
For example, this may range from 19.5 ms to 5.0 s when
using an oscillator frequency of 16 MHz.
Table 27 lists the resolution and the maximum time interval
of the Watchdog Timer using different system clocks.
The Watchdog Timer is controlled by the Watchdog control
bits:
EW2; DFCON.7 (SFR address C0H)
EW1; PWM10H.7 (SFR address C6H)
EW0; PWM10L.7 (SFR address C6H).
Only when EW2 to EW0 = 101 the Watchdog Timer is
disabled and allows the Power-down mode to be enabled.
The rest of pattern combinations will keep the Watchdog
Timer enabled and disable the Power-down mode.
This security key with multiple flags split in two SFRs will
prevent the Watchdog Timer from being terminated
abnormally when the function of the Watchdog Timer is
needed.
t
t
1
--256
×
=
Table 27
Resolution and the maximum time interval of the WDT
f
clk
(MHz)
PRESCALER FACTOR
RESOLUTION
(ms)
MAXIMUM TIME INTERVAL
(s)
10
12
16
152
15.56
12.97
19.46
4.0
3.3
5.0
304
相关PDF资料
PDF描述
P87C380 Microcontrollers for monitors with DDC interface, auto-sync detection and sync proc(带DDC接口,同步监测和同步处理的监视器微控制器)
P83C880 Microcontrollers for monitors with DDC interface, auto-sync detection and sync proc(带DDC接口,同步监测和同步处理的监视器微控制器)
P83C180 Microcontrollers for monitors with DDC interface, auto-sync detection and sync proc(带DDC接口,同步监测和同步处理的监视器微控制器)
P83C370AAR Microcontrollers for PAL/SECAM TV with OSD and VST(带 OSD和 VST的在PAL/SECAM TV中应用的微控制器)
P83C570AAR Microcontrollers for NTSC TVs with On-Screen Display OSD and Closed Caption CC
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