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参数资料
| 型号： | P83C570 |
| 厂商： | NXP Semiconductors N.V. |
| 英文描述： | Microcontrollers for NTSC TVs with On-Screen Display OSD and Closed Caption CC |
| 中文描述： | 微控制器用于NTSC电视的屏幕显示OSD和字幕消委会 |
| 文件页数： | 34/80页 |
| 文件大小： | 266K |
| 代理商： | P83C570 |
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1999 Jun 11
34
Philips Semiconductors
Product specification
Microcontrollers for NTSC TVs with On-Screen
Display (OSD) and Closed Caption (CC)
P8xCx70 family
17 DATA SLICER AND CC COMMAND INTERPRETER
The P8xCx70 family contains a Data Slicer which slices
Closed Caption data from the CVBS signal. The slice line
is programmable between lines 17 to 23. CC command
interpretation has to be done by a Command Interpreter
which is a relocatable software module. It interprets the
2 bytes that have been sliced off the selected CVBS line
and prepares the display RAM in the OSD block for proper
Closed Caption and OSD display function.
The composite data signal contained within the active
portion of the CVBS line consists of a 7 cycle sine-wave
clock run-in burst, 3 start bits and 16 bits of data. These
16 bits consist of two 8-bit alphanumeric characters
formulated according to the American Standard Code for
Information Interchange (ASCII; x3.4-1967) with odd
parity. The clock rate is 0.5035 MHz which is 32f
h
(horizontal frequency). The clock run-in burst data packet
is 50 IRE units (peak-to-peak). Data is sent with the LSB
(bit D0) being sent first and the MSB (bit D7, the parity bit)
sent last. Figure 13 illustrates CVBS timing.
17.1
Data Slicer
The Composite Video Baseband Signal input should be a
signal which is nominally 1 V
(p-p)
with sync tips negative
and band limited to
±
3% of the standard frequency.
The Data Slicer consists of:
7-bit ADC which converts the analog CVBS signal into
digital data for extraction
Sync separator and bit clock recovery
Data Detector, which extracts the serial stream of bits
from the video signal
Byte Extractor, which performs serial-to-parallel
conversion.
17.1.1
A
NALOG
-
TO
-D
IGITAL
C
ONVERTER
A 7-bit ADC generates a clean CMOS level data signal by
slicing the analog CVBS signal using a 6 MHz clock. The
ADC error is
±
1
2
LSB across the full range (2 V
(p-p)
).
17.1.2
S
YNC SEPARATION AND ACQUISITION TIMING
This block contains an acquisition phase-locked loop
which locks onto the incoming video line syncs, with a
frequency error of
±
3% for a varying frequency error and a
wide locking range, such as a VCR.
It also provides a line rate ramp, from which the line based
timing signals for the data detection section may be
decoded.
17.1.3
D
ATA
D
ETECTOR
The data detector consists of a low-pass filter which
screens out signals above 1 MHz (mainly noise); a
DC-loop, which removes DC offset and low frequency
interference and adjusts the slice level continuously; an
amplitude estimator, which provides the DC-loop with an
estimation of signal strength to enable an accurate
adaptive slicing level to be calculated and also aids in the
detection of signal loss or absence of Closed Caption data
and a clock synchronizer, which provides accurate
centre-on-the-incoming data bits clock to the byte
extractor.
17.1.4
B
YTE EXTRACTOR
The Byte extractor extracts data bytes from the sliced bit
stream using the clock provided by the data detector block,
performs serial-to-parallel conversion, then feeds the
2 data bytes to a pair of registers (CCData1 and CCData2)
which hold the 2 data bytes for CC command
interpretation. At the end of the selected CVBS line the
byte extractor will issue the CC interrupt to the CPU. This
interrupt will be generated regardless of whether new data
has been received or not.
17.2
Command Interpreter
The Command Interpreter is implemented in software. It is
used for data field selection, code interpretation and
addressing of the display RAM. It reads the CCData1 and
CCData2 registers, checks for the correct parity, field and
channel number. When the data received is the correct
data, the bytes are passed on to the logic decoder
software that interprets the data and addresses the display
RAM. The CC770 Closed Caption software supports the
three main modes CAPTION, TEXT and XDS. These
operation modes can be selected by the user. For the first
two modes, the data reception will be done in one of two
operating channels C1 or C2 separately for Field 1 or
Field 2 of the video frame. The XDS mode is only available
in Field 2.
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| P83C770 | Microcontrollers for NTSC TVs with On-Screen Display (OSD) and Closed Caption (CC)(在NTSC TV中应用的具有屏幕显示和字幕关闭特点的微控制器) |
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相关代理商/技术参数 |
参数描述 |
|---|---|
| P83C570AAR | 制造商:PHILIPS 制造商全称:NXP Semiconductors 功能描述:Microcontrollers for NTSC TVs with On-Screen Display OSD and Closed Caption CC |
| P83C575EBA | 制造商:未知厂家 制造商全称:未知厂家 功能描述:8-Bit Microcontroller |
| P83C575EBAA | 制造商:PHILIPS 制造商全称:NXP Semiconductors 功能描述:80C51 8-bit microcontroller family 8K/256 OTP/ROM/ROMless, 4 comparator, failure detect circuitry, watchdog timer |
| P83C575EBB | 制造商:未知厂家 制造商全称:未知厂家 功能描述:8-Bit Microcontroller |
| P83C575EBBB | 制造商:PHILIPS 制造商全称:NXP Semiconductors 功能描述:80C51 8-bit microcontroller family 8K/256 OTP/ROM/ROMless, 4 comparator, failure detect circuitry, watchdog timer |
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