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参数资料
| 型号： | P83C576EBAA |
| 厂商： | NXP SEMICONDUCTORS |
| 元件分类： | 微控制器/微处理器 |
| 英文描述： | 80C51 8-bit microcontroller family 8K/256 OTP/ROM, 6 channel 10-bit A/D, 4 comparators, failure detect circuitry, watchdog timer |
| 中文描述： | 8-BIT, MROM, 16 MHz, MICROCONTROLLER, PQCC44 |
| 封装： | PLASTIC, MO-047AC, SOT-187-2, LCC-44 |
| 文件页数： | 17/46页 |
| 文件大小： | 447K |
| 代理商： | P83C576EBAA |
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Philips Semiconductors
Product specification
83C576/87C576
80C51 8-bit microcontroller family
8K/256 OTP/ROM, 6 channel 10-bit A/D, 4 comparators,
failure detect circuitry, watchdog timer
1998 Jun 04
17
WATCHDOG TIMER
The watchdog timer is not directly loadable by the user. Instead, the
value to be loaded into the main timer is held in an autoload register
or is part of the mask ROM programming. In order to cause the main
timer to be loaded with the appropriate value, a special sequence of
software action must take place. This operation is referred to as
feeding the watchdog timer.
To feed the watchdog, two instructions must be sequentially
executed successfully. No intervening instruction fetches are
allowed, so interrupts should be disabled before feeding the
watchdog. The instructions should move A5H to the WFEED1
register and then 5AH to the WFEED2 register. If WFEED1 is
correctly loaded and WFEED2 is not correctly loaded, then an
immediate underflow will occur.
The watchdog timer subsystem has two modes of operation. Its
principal function is a watchdog timer. In this mode it protects the
system from incorrect code execution by causing a system reset
when the watchdog timer underflows as a result of a failure of
software to feed the timer prior to the timer reaching its terminal
count. If the user does not employ the watchdog function, the
watchdog subsystem can be used as a timer. In this mode, reaching
the terminal count sets a flag. In most other respects, the timer
mode possesses the characteristics of the watchdog mode. This is
done to protect the integrity of the watchdog function.
The watchdog timer subsystem consists of a prescaler and a main
counter. The prescaler has 8 selectable taps off the final stages and
the output of a selected tap provides the clock to the main counter.
The main counter is the section that is loaded as a result of the
software feeding the watchdog and it is the section that causes the
system reset (watchdog mode) or time-out flag to be set (timer
mode) if allowed to reach its terminal count.
Programming the Watchdog Timer
Both the EPROM and ROM devices have a set of SFRs for holding
the watchdog autoload values and the control bits. The watchdog
time-out flag is present in the PCON register and operates the same
in all versions. In the EPROM device, the watchdog parameters
(autoload value and control) are always taken from the SFRs. In the
ROM device, the watchdog parameters can be mask programmed
or taken from the SFRs. The selection to take the watchdog
parameters from the SFRs or from the mask programmed values is
controlled by EA (external access). When EA is high (internal ROM
access), the watchdog parameters are taken from the mask
programmed values. If the watchdog is mask programmed to the
timer mode, then the autoload values and the pre-scaler taps are
taken from the SFRs. When EA is low (external access), the
watchdog parameters are taken from the SFRs. The user should be
able to leave code in his program which initializes the watchdog
SFRs even though he has migrated to the mask ROM part. This
allows no code changes from EPROM prototyping to ROM coded
production parts. The run control bit only functions in timer mode
and does not require a feed sequence to modify.
Watchdog Detailed Operation
EPROM Device (and ROMless Operation: EA = 0)
In the ROMless operation (ROM part, EA = 0) and in the EPROM
device, the watchdog operates in the following manner (see
Figure 15).
Whether the watchdog is in the watchdog or timer mode, when
external RESET is applied, the following takes place:
Watchdog mode bit set to watchdog mode.
Watchdog is running.
Autoload register set to 00 (min. count).
Watchdog time-out flag is unchanged.
Prescaler is cleared.
Prescaler tap set to the highest divide.
Autoload takes place.
The watchdog can be fed even though it is in the timer mode.
Note that the operational concept is for the watchdog mode of
operation, when coming out of a hardware reset, the software
should load the autoload registers, set the mode to watchdog, clear
the watchdog timeout flag, and then feed the watchdog (cause an
autoload). The watchdog will now be starting at a known point.
If the watchdog is in the watchdog mode and running and happens
to underflow at the time the external RESET is applied, the
watchdog time-out flag will be set.
When the watchdog is in the watchdog mode and the watchdog
underflows, the following action takes place (see Figure 17):
Autoload takes place.
Watchdog time-out flag is set
Mode bit unchanged.
Watchdog run bit unchanged.
Autoload register unchanged.
Prescaler tap unchanged.
All other device action same as external reset.
Note that if the watchdog underflows, the program counter will start
from 00H as in the case of an external reset. The watchdog time-out
flag can be examined to determine if the watchdog has caused the
reset condition. The watchdog time-out flag bit must be cleared by
software.
When the watchdog is in the timer mode and the timer software
underflows, the following action takes place:
Autoload takes place.
Watchdog time-out flag is set
Mode bit unchanged.
Watchdog run bit unchanged.
Autoload register unchanged.
Prescaler tap unchanged.
Mask ROM Device (EA = 1)
In the mask ROM device, the watchdog mode bit (WDMOD) is mask
programmed and the bit in the watchdog command register is read
only and reflects the mask programmed selection. If the mask
programmed mode bit selects the timer mode, then the watchdog
run bit (WDRUN) operates as described under EPROM Device. If the
mask programmed bit selects the watchdog mode, then the watchdog
run bit has no effect on the timer operation (see Figure 16).
Watchdog Function
The watchdog consists of a programmable prescaler and the main
timer. The prescaler derives its clock from the on-chip oscillator. The
prescaler consists of a divide by 2 followed by a 13 stage upcounter
with taps from stage 6 through stage 13. This is shown in Figure 18.
相关PDF资料 |
PDF描述 |
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| P83C576EHPN | 80C51 8-bit microcontroller family 8K/256 OTP/ROM, 6 channel 10-bit A/D, 4 comparators, failure detect circuitry, watchdog timer |
| P87C576EHPN | 80C51 8-bit microcontroller family 8K/256 OTP/ROM, 6 channel 10-bit A/D, 4 comparators, failure detect circuitry, watchdog timer |
| P83C576EBBB | 80C51 8-bit microcontroller family 8K/256 OTP/ROM, 6 channel 10-bit A/D, 4 comparators, failure detect circuitry, watchdog timer |
| P87C576EBBB | 80C51 8-bit microcontroller family 8K/256 OTP/ROM, 6 channel 10-bit A/D, 4 comparators, failure detect circuitry, watchdog timer |
| P87C576EBAA | 80C51 8-bit microcontroller family 8K/256 OTP/ROM, 6 channel 10-bit A/D, 4 comparators, failure detect circuitry, watchdog timer |
相关代理商/技术参数 |
参数描述 |
|---|---|
| P83C576EBB | 制造商:未知厂家 制造商全称:未知厂家 功能描述:8-Bit Microcontroller |
| P83C576EBBB | 制造商:PHILIPS 制造商全称:NXP Semiconductors 功能描述:80C51 8-bit microcontroller family 8K/256 OTP/ROM, 6 channel 10-bit A/D, 4 comparators, failure detect circuitry, watchdog timer |
| P83C576EBN | 制造商:未知厂家 制造商全称:未知厂家 功能描述:Microcontroller |
| P83C576EBP | 制造商:未知厂家 制造商全称:未知厂家 功能描述:8-Bit Microcontroller |
| P83C576EBPN | 制造商:PHILIPS 制造商全称:NXP Semiconductors 功能描述:80C51 8-bit microcontroller family 8K/256 OTP/ROM, 6 channel 10-bit A/D, 4 comparators, failure detect circuitry, watchdog timer |
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