- 您现在的位置：买卖IC网 > PDF目录367738 > P83C654EFP (NXP Semiconductors N.V.) CONN HEADER 11POS SGL PCB 30GOLD PDF资料下载
参数资料
| 型号： | P83C654EFP |
| 厂商： | NXP Semiconductors N.V. |
| 英文描述： | CONN HEADER 11POS SGL PCB 30GOLD |
| 中文描述： | CMOS单芯片8位微控制器 |
| 文件页数： | 11/88页 |
| 文件大小： | 497K |
| 代理商： | P83C654EFP |
第1页第2页第3页第4页第5页第6页第7页第8页第9页第10页当前第11页第12页第13页第14页第15页第16页第17页第18页第19页第20页第21页第22页第23页第24页第25页第26页第27页第28页第29页第30页第31页第32页第33页第34页第35页第36页第37页第38页第39页第40页第41页第42页第43页第44页第45页第46页第47页第48页第49页第50页第51页第52页第53页第54页第55页第56页第57页第58页第59页第60页第61页第62页第63页第64页第65页第66页第67页第68页第69页第70页第71页第72页第73页第74页第75页第76页第77页第78页第79页第80页第81页第82页第83页第84页第85页第86页第87页第88页
Philips Semiconductors
Product data
P83C654X2/P87C654X2
80C51 8-bit microcontroller family
16 kB OTP/ROM,
256B RAM, low voltage (2.7 to 5.5 V), low power, high speed
(30/33 MHz)
2004 Apr 20
11
OSCILLATOR CHARACTERISTICS
XTAL1 and XTAL2 are the input and output, respectively, of an
inverting amplifier. The pins can be configured for use as an
on-chip oscillator.
To drive the device from an external clock source, XTAL1 should be
driven while XTAL2 is left unconnected. Minimum and maximum
high and low times specified in the data sheet must be observed.
This device is configured at the factory to operate using 12 clock
periods per machine cycle, referred to in this datasheet as “12-clock
mode”. It may be optionally configured on commercially available
EPROM programming equipment to operate at 6 clocks per machine
cycle, referred to in this datasheet as “6-clock mode”. (This yields
performance equivalent to twice that of standard 80C51 family
devices). Also see next page.
RESET
A reset is accomplished by holding the RST pin HIGH for at least
two machine cycles (12 oscillator periods in 6-clock mode, or 24
oscillator periods in 12-clock mode), while the oscillator is running.
To insure a good power-on reset, the RST pin must be HIGH long
enough to allow the oscillator time to start up (normally a few
milliseconds) plus two machine cycles. At power-on, the voltage on
V
CC
and RST must come up at the same time for a proper start-up.
Ports 1, 2, and 3 will asynchronously be driven to their reset
condition when a voltage above V
IH (min.)
is applied to RESET. The
value on the EA pin is latched when RST is deasserted and has no
further effect.
LOW POWER MODES
Stop Clock Mode
The static design enables the clock speed to be reduced down to
0 MHz (stopped). When the oscillator is stopped, the RAM and
Special Function Registers retain their values. This mode allows
step-by-step utilization and permits reduced system power
consumption by lowering the clock frequency down to any value. For
lowest power consumption the Power-down mode is suggested.
Idle Mode
In the idle mode (see Table 2), the CPU puts itself to sleep while all
of the on-chip peripherals stay active. The instruction to invoke the
idle mode is the last instruction executed in the normal operating
mode before the idle mode is activated. The CPU contents, the
on-chip RAM, and all of the special function registers remain intact
during this mode. The idle mode can be terminated either by any
enabled interrupt (at which time the process is picked up at the
interrupt service routine and continued), or by a hardware reset
which starts the processor in the same manner as a power-on reset.
Power-Down Mode
To save even more power, a Power-down mode (see Table 2) can
be invoked by software. In this mode, the oscillator is stopped and
the instruction that invoked power-down is the last instruction
executed. The on-chip RAM and Special Function Registers retain
their values down to 2 V and care must be taken to return V
CC
to the
minimum specified operating voltages before the Power-down mode
is terminated.
Either a hardware reset or external interrupt can be used to exit from
power-down. Reset redefines all the SFRs but does not change the
on-chip RAM. An external interrupt allows both the SFRs and the
on-chip RAM to retain their values.
To properly terminate power-down, the reset or external interrupt
should not be executed before V
CC
is restored to its normal
operating level and must be held active long enough for the
oscillator to restart and stabilize (normally less than 10 ms).
With an external interrupt, INT0 and INT1 must be enabled and
configured as level-sensitive. Holding the pin LOW restarts the
oscillator but bringing the pin back HIGH completes the exit. Once
the interrupt is serviced, the next instruction to be executed after
RETI will be the one following the instruction that put the device into
power-down.
POWER-OFF FLAG
The Power-Off Flag (POF) is set by on-chip circuitry when the V
CC
level on the P8xC654X2 rises from 0 to 5 V. The POF bit can be set
or cleared by software allowing a user to determine if the reset is the
result of a power-on or a warm start after power-down. The V
CC
level must remain above 3 V for the POF to remain unaffected by
the V
CC
level.
Low-Power EPROM operation (LPEP)
The EPROM array contains some analog circuits that are not
required when V
CC
is less than 4 V, but are required for a V
CC
greater than 4 V. The LPEP bit (AUXR.4), when set, will power-down
these analog circuits resulting in a reduced supply current. This bit
should be set ONLY for applications that operate at a V
CC
less than
4 V.
Design Consideration
When the idle mode is terminated by a hardware reset, the device
normally resumes program execution, from where it left off, up to
two machine cycles before the internal reset algorithm takes control.
On-chip hardware inhibits access to internal RAM in this event, but
access to the port pins is not inhibited. To eliminate the possibility of
an unexpected write when Idle is terminated by reset, the instruction
following the one that invokes Idle should not be one that writes to a
port pin or to external memory.
ONCE
Mode
The ONCE (“On-Circuit Emulation”) Mode facilitates testing and
debugging of systems without the device having to be removed from
the circuit. The ONCE Mode is invoked by:
1. Pull ALE LOW while the device is in reset and PSEN is HIGH;
2. Hold ALE LOW as RST is deactivated.
While the device is in ONCE Mode, the Port 0 pins go into a float
state, and the other port pins and ALE and PSEN are weakly pulled
HIGH. The oscillator circuit remains active. While the device is in
this mode, an emulator or test CPU can be used to drive the circuit.
Normal operation is restored when a normal reset is applied.
Programmable Clock-Out
A 50 % duty cycle clock can be programmed to come out on P1.0.
This pin, besides being a regular I/O pin, has two alternate
functions. It can be programmed:
1. to input the external clock for Timer/Counter 2, or
2. to output a 50 % duty cycle clock ranging from 122 Hz to 8 MHz at
a 16 MHz operating frequency (61 Hz to 4 MHz in 12-clock mode).
To configure the Timer/Counter 2 as a clock generator, bit C/T2 (in
T2CON) must be cleared and bit T20E in T2MOD must be set. Bit
TR2 (T2CON.2) also must be set to start the timer.
相关PDF资料 |
PDF描述 |
|---|---|
| P83C654EFPN | CONN HEADER 13POS SGL PCB 30GOLD |
| P83C654EHA | CMOS single-chip 8-bit microcontroller |
| P83C654EHAA | CMOS single-chip 8-bit microcontroller |
| P83C654EHB | CMOS single-chip 8-bit microcontroller |
| P83C654EHBB | CMOS single-chip 8-bit microcontroller |
相关代理商/技术参数 |
参数描述 |
|---|---|
| P83C654EFPN | 制造商:PHILIPS 制造商全称:NXP Semiconductors 功能描述:CMOS single-chip 8-bit microcontroller |
| P83C654EHA | 制造商:PHILIPS 制造商全称:NXP Semiconductors 功能描述:CMOS single-chip 8-bit microcontroller |
| P83C654EHAA | 制造商:PHILIPS 制造商全称:NXP Semiconductors 功能描述:CMOS single-chip 8-bit microcontroller |
| P83C654EHB | 制造商:PHILIPS 制造商全称:NXP Semiconductors 功能描述:CMOS single-chip 8-bit microcontroller |
| P83C654EHBB | 制造商:PHILIPS 制造商全称:NXP Semiconductors 功能描述:CMOS single-chip 8-bit microcontroller |
发布紧急采购，3分钟左右您将得到回复。