参数资料
型号: P83C654FBB
厂商: NXP SEMICONDUCTORS
元件分类: 微控制器/微处理器
英文描述: CMOS single-chip 8-bit microcontroller
中文描述: 8-BIT, MROM, 16 MHz, MICROCONTROLLER, PQFP44
文件页数: 6/88页
文件大小: 497K
代理商: P83C654FBB
Philips Semiconductors
Product data
P83C654X2/P87C654X2
80C51 8-bit microcontroller family
16 kB OTP/ROM,
256B RAM, low voltage (2.7 to 5.5 V), low power, high speed
(30/33 MHz)
2004 Apr 20
6
PIN DESCRIPTIONS
MNEMONIC
PIN NUMBER
TYPE
NAME AND FUNCTION
PLCC
LQFP
V
SS
V
CC
P0.0–0.7
2
22
16
I
Ground:
0 V reference.
44
38
I
Power Supply:
This is the power supply voltage for normal, idle, and power-down operation.
43–36
37–30
I/O
Port 0:
Port 0 is an open-drain, bidirectional I/O port. Port 0 pins that have 1s written to them
float and can be used as high-impedance inputs. Port 0 is also the multiplexed low-order
address and data bus during accesses to external program and data memory. In this
application, it uses strong internal pull-ups when emitting 1s.
P1.0–P1.7
2
2–9
40–44,
1–3
I/O
Port 1:
Port 1 is an 8-bit bidirectional I/O port with internal pull-ups on all pins. Port 1 pins that
have 1s written to them are pulled HIGH by the internal pull-ups and can be used as inputs. As
inputs, port 1 pins that are externally pulled LOW will source current because of the internal
pull-ups. (See DC Electrical Characteristics: I
IL
).
Alternate functions for P8xC654X2 Port 1 include:
T2 (P1.0):
Timer/Counter 2 external count input/Clockout (see Programmable Clock-Out)
T2EX (P1.1):
Timer/Counter 2 Reload/Capture/Direction Control
2
3
3
4
5
6
7
8
9
40
41
41
42
43
44
1
2
3
I/O
I
I
I
I/O
I/O
I/O
I/O
I/O
SCL (P1.6):
I
2
C-bus clock line (open drain)
SDA (P1.7):
I
2
C-bus data line (open drain)
P2.0–P2.7
2
24–31
18–25
I/O
Port 2:
Port 2 is an 8-bit bidirectional I/O port with internal pull-ups. Port 2 pins that have 1s
written to them are pulled HIGH by the internal pull-ups and can be used as inputs. As inputs,
port 2 pins that are externally being pulled LOW will source current because of the internal
pull-ups. (See DC Electrical Characteristics: I
IL
). Port 2 emits the high-order address byte
during fetches from external program memory and during accesses to external data memory
that use 16-bit addresses (MOVX @DPTR). In this application, it uses strong internal pull-ups
when emitting 1s. During accesses to external data memory that use 8-bit addresses (MOV
@Ri), port 2 emits the contents of the P2 special function register.
P3.0–P3.7
2
11,
13–19
5, 7–13
I/O
Port 3:
Port 3 is an 8-bit bidirectional I/O port with internal pull-ups. Port 3 pins that have 1s
written to them are pulled HIGH by the internal pull-ups and can be used as inputs. As inputs,
port 3 pins that are externally being pulled LOW will source current because of the pull-ups.
(See DC Electrical Characteristics: I
IL
). Port 3 also serves the special features of the
P8xC654X2, as listed below:
RxD (P3.0):
Serial input port
TxD (P3.1):
Serial output port
INT0 (P3.2):
External interrupt 0
INT1 (P3.3):
External interrupt 1
T0 (P3.4):
Timer 0 external input
T1 (P3.5):
Timer 1 external input
WR (P3.6):
External data memory write strobe
RD (P3.7):
External data memory read strobe
11
13
14
15
16
17
18
19
5
7
8
9
10
11
12
13
I
O
I
I
I
I
O
O
RST
2
10
4
I
Reset:
A HIGH on this pin for two machine cycles while the oscillator is running, resets the
device. An internal diffused resistor to V
SS
permits a power-on reset using only an external
capacitor to V
CC
.
Address Latch Enable:
Output pulse for latching the LOW byte of the address during an
access to external memory. In normal operation, ALE is emitted at constant rate of 1/6 the
oscillator frequency in 12x clock mode, 1/3 the oscillator frequency in 6x clock mode, and can
be used for external timing or clocking. Note that one ALE pulse is skipped during each access
to external data memory. ALE can be disabled by setting SFR auxiliary.0. With this bit set, ALE
will be active only during a MOVX instruction.
ALE
2
33
27
O
PSEN
2
32
26
O
Program Store Enable:
The read strobe to external program memory. When executing code
from the external program memory, PSEN is activated twice each machine cycle, except that
two PSEN activations are skipped during each access to external data memory. PSEN is not
activated during fetches from internal program memory.
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