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| 型号： | P83C766BDP |
| 厂商： | NXP SEMICONDUCTORS |
| 元件分类： | 微控制器/微处理器 |
| 英文描述： | Microcontrollers for PAL/SECAM TV with OSD and VST |
| 中文描述： | 8-BIT, MROM, 12 MHz, MICROCONTROLLER, PDIP42 |
| 封装： | 0.600 INCH, PLASTIC, SDIP-42 |
| 文件页数： | 35/92页 |
| 文件大小： | 382K |
| 代理商： | P83C766BDP |
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1999 Mar 10
35
Philips Semiconductors
Product specification
Microcontrollers for PAL/SECAM TV
with OSD and VST
P8xCx66 family
15 ANALOG CONTROL
The P8xCx66 has nine Pulse Width Modulated (PWM)
outputs for analog control purposes e.g., volume, balance,
brightness, voltage synthesized tuning etc. Each PWM
output generates a pulse pattern with a programmable
duty cycle.
The nine PWM outputs are specified below:
8 PWM outputs with 7-bit resolution (PWM0 to PWM7)
1 PWM output with 14-bit resolution (TPWM).
The 7-bit PWM outputs are described in Section 15.1 and
the 14-bit PWM output is described in Section 15.2.
15.1
7-bit PWM outputs (PWM0 to PWM7)
The block diagram of a typical 7-bit PWM circuit is shown
in Fig.19.
PWM outputs PWM0 to PWM7 share the same pins as
general I/O port lines P5.1 to P5.7 and P3.3 respectively.
Selection of the pin function as either a PWM output or
general I/O port line is achieved by setting the PWMnE bit
in the associated PWM register (where n = 0 to 7).
The PWM registers are shown in Table 38.
The clock frequency of each PWM circuit is
1
4
f
osc
and
therefore the repetition frequency of each 7-bit PWM
output is
1
512
f
osc
.
The polarity of each PWM output is fixed active HIGH.
The HIGH period of each PWM output is dependent upon
the contents of the PWM data latch and may be calculated
as shown below:
where (PWMn) is the decimal value held in the PWMn data
latch
The PWM output analog value is determined by the ratio
of the HIGH period and the repetition period. A DC voltage
proportional to the PWM control setting is obtained by
means of an external integration network (low-pass filter)
connected to the PWM output pin.
The rising edge of each of the 8 PWM outputs is separated
by one
1
4
f
osc
cycle, this is shown in Fig.21. PWM1 will
always start at ‘2’, and PWM5 will start at ‘6’ independent
of other PWMs value.
Figure 20 shows active HIGH PWM output patterns.
t
HIGH
4
PWMn
f
osc
(
)
×
=
Table 38
7-bit PWM data registers
REGISTER
ADDRESS
7
6
5
4
3
2
1
0
PWM0
PWM1
PWM2
PWM3
PWM4
PWM5
PWM6
PWM7
E4H
E5H
E6H
E7H
ECH
EDH
EEH
EFH
PWM0E
PWM1E
PWM2E
PWM3E
PWM4E
PWM5E
PWM6E
PWM7E
data6
data6
data6
data6
data6
data6
data6
data6
data5
data5
data5
data5
data5
data5
data5
data5
data4
data4
data4
data4
data4
data4
data4
data4
data3
data3
data3
data3
data3
data3
data3
data3
data2
data2
data2
data2
data2
data2
data2
data2
data1
data1
data1
data1
data1
data1
data1
data1
data0
data0
data0
data0
data0
data0
data0
data0
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