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参数资料
| 型号： | P83CL884T |
| 厂商： | NXP Semiconductors N.V. |
| 英文描述： | TELX microcontrollers for CT0 handset/basestation applications |
| 中文描述： | TELX微控制器CT0手机/基站应用 |
| 文件页数： | 18/32页 |
| 文件大小： | 145K |
| 代理商： | P83CL884T |
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18
Philips Semiconductors
Product specification
TELX microcontrollers for CT0
handset/basestation applications
P8xCL883; P8xCL884
6.6.2.2
Mode entry
The In-System Programming mode is entered by setting
the InSysMode bit of the OISYS SFR. The I
2
C-bus is used
for data transfer in this mode. If the I
2
C-bus interface is
addressed by an external master, the interface generates
an interrupt request. The interrupt handler can now read
the OISYS SFR and determine the status of the external
high voltage (VPon). If high voltage is not present the
interrupt is a standard I
2
C-bus interrupt.
If high voltage is present the In-System Program interrupt
routine has to start that writes the InSysMode bit
(OISYS.0) and controls the address and data transfer.
This paragraph is valid for version 2 (‘2’ ending on
type number).
During In-System Programming the OTP
memory must be in the DC read mode. This is achieved by
writing 08H to the OTEST SFR. If the In-System
Programming mode is left, 00H must be written into the
OTEST SRF.
The program voltage must be available and stable for at
least 10
μ
s before the mode is entered and has to be
stable until the circuit has left the In-System Programming
mode. The high voltage can be applied for maximum
60 seconds during the complete lifetime of the circuit.
6.6.2.3
Program cycle
The data and address must be supplied to the
microcontroller and the control program must write to the
SFRs: ODATA, OAH and OAL. A timer has to be initialized
for a 100
μ
s cycle and the WE bit of the OISYS SFR must
be set. Now the core has to be set into Idle mode. As long
as the circuit is in idle mode a programming pulse is
applied. After the interrupt request of the timer the OTP is
available for normal code fetching.
The address applied to the OAH and OAL SFRs must be
in the 8 kbytes address space.
6.6.2.4
Verify for In-System Programming
Verify is done in similar way as programming. The circuit
is put into Idle mode and at the start of this mode the sense
amplifiers are switched to verify mode and a read cycle is
started. The timer must be initialized for a cycle of at least
1
μ
s. The address is supplied by the SFRs OAH and OAL.
The WE bit of the OISYS SFR has to be reset. The OTP
output data is latched in the ODATA SFR. After Idle mode
is finished this SFR can be read in a normal way.
To ensure that the verified data is written into the SFR it is
advised to write FFH into the ODATA SFR before a verify
is started.
6.6.2.5
Signature bytes
The signature bytes can be read by setting the SIG bit of
the OISYS SFR and applying the address of the signature
byte. Applying a write pulse while the SIG bit of the OISYS
SFR is HIGH is forbidden although the contents of the
signature bytes will never be destroyed.
6.6.2.6
How to connect the PORENABLE/V
PP
pin in
the In-System Programming mode
If the V
PP
pin is dual-mode (e.g. PORENABLE/V
PP
), ICs
connected to the signal PORENABLE
must be able to
withstand up to 13 V
, i.e. cannot have clamping diodes or
low break-down voltages. If the pin is connected to a fixed
voltage (V
DD
or V
SS
) there must be a way of switching-off
this connection on the PCB. One possible implementation
is presented in Fig.7 where POR is enabled in normal
mode of operation (pin PORENABLE/V
PP
= 1 by the
pull-up), the V
PP
source must supply enough current in R
p
in order to guarantee a minimum 12.5 V on the
PORENABLE/V
PP
pin.
Note that if in the application the Power-on reset is
disabled (pin PORENABLE/V
PP
= 0), applying a high
voltage to the PORENABLE/V
PP
pin will also enable the
POR circuit. This will cause a reset independent of the
actual V
DD
value.
6.7
Oscillator circuitry
General information on the oscillator circuitry can be found
in the “TELX family”data sheet.
6.7.1
R
ESONATOR REQUIREMENTS
For correct function of the oscillator, the values of R
1
and
C
0
of the chosen resonator (quartz or PXE) must be below
the line shown in Fig.8a. The value of the parallel resistor
R
0
must be less than 47 k
.
The wiring between chip and resonator should be kept as
short as possible.
6.7.2
R
ECOMMENDED RESONATOR TYPES
CSA 3.58MG (supplier Murata)
FCR3.58M5 (supplier TDK).
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相关代理商/技术参数 |
参数描述 |
|---|---|
| P83CL884T/XXX | 制造商:未知厂家 制造商全称:未知厂家 功能描述:8-Bit Microcontroller |
| P83LPC912FDHCV961, | 功能描述:8位微控制器 -MCU P83LPC912FDH/TSSOP14/REEL13//C RoHS:否 制造商:Silicon Labs 核心:8051 处理器系列:C8051F39x 数据总线宽度:8 bit 最大时钟频率:50 MHz 程序存储器大小:16 KB 数据 RAM 大小:1 KB 片上 ADC:Yes 工作电源电压:1.8 V to 3.6 V 工作温度范围:- 40 C to + 105 C 封装 / 箱体:QFN-20 安装风格:SMD/SMT |
| P83LPC913FDH/CV960 | 功能描述:8位微控制器 -MCU P83LPC913FDH/TSSOP14/REEL13//C RoHS:否 制造商:Silicon Labs 核心:8051 处理器系列:C8051F39x 数据总线宽度:8 bit 最大时钟频率:50 MHz 程序存储器大小:16 KB 数据 RAM 大小:1 KB 片上 ADC:Yes 工作电源电压:1.8 V to 3.6 V 工作温度范围:- 40 C to + 105 C 封装 / 箱体:QFN-20 安装风格:SMD/SMT |
| P83LPC913FDH/CV962 | 功能描述:8位微控制器 -MCU P83LPC913FDH/TSSOP14/REEL13//C RoHS:否 制造商:Silicon Labs 核心:8051 处理器系列:C8051F39x 数据总线宽度:8 bit 最大时钟频率:50 MHz 程序存储器大小:16 KB 数据 RAM 大小:1 KB 片上 ADC:Yes 工作电源电压:1.8 V to 3.6 V 工作温度范围:- 40 C to + 105 C 封装 / 箱体:QFN-20 安装风格:SMD/SMT |
| P83LPC930FDH/CV962 | 功能描述:8位微控制器 -MCU P83LPC930FDH/TSSOP28/TUBESM//C RoHS:否 制造商:Silicon Labs 核心:8051 处理器系列:C8051F39x 数据总线宽度:8 bit 最大时钟频率:50 MHz 程序存储器大小:16 KB 数据 RAM 大小:1 KB 片上 ADC:Yes 工作电源电压:1.8 V to 3.6 V 工作温度范围:- 40 C to + 105 C 封装 / 箱体:QFN-20 安装风格:SMD/SMT |
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