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参数资料
| 型号： | P87C51RC2FA,512 |
| 厂商： | NXP Semiconductors |
| 文件页数： | 29/67页 |
| 文件大小： | 0K |
| 描述： | IC 80C51 MCU 512 RAM 44-PLCC |
| 产品培训模块： | Migrating from 8/16-Bit MCUs to 32-Bit ARMs |
| 标准包装： | 26 |
| 系列： | 87C |
| 核心处理器： | 8051 |
| 芯体尺寸： | 8-位 |
| 速度： | 33MHz |
| 连通性： | EBI/EMI，UART/USART |
| 外围设备： | POR，PWM，WDT |
| 输入/输出数： | 32 |
| 程序存储器容量： | 32KB（32K x 8） |
| 程序存储器类型： | OTP |
| RAM 容量： | 512 x 8 |
| 电压 - 电源 (Vcc/Vdd)： | 2.7 V ~ 5.5 V |
| 振荡器型： | 内部 |
| 工作温度： | -40°C ~ 85°C |
| 封装/外壳： | 44-LCC（J 形引线） |
| 包装： | 管件 |
| 产品目录页面： | 705 (CN2011-ZH PDF) |
| 其它名称： | 568-4514-5 935272107512 P87C51RC2FA P87C51RC2FA-ND |
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Philips Semiconductors
Product data
P87C51RA2/RB2/RC2/RD2
80C51 8-bit microcontroller family 8KB/16KB/32KB/64KB OTP
with 512B/1KB RAM, low voltage (2.7 to 5.5 V), low power, high
speed (30/33 MHz)
2003 Jan 24
35
CMOD Address = D9H
Reset Value = 00XX X000B
CIDL
WDTE
–
CPS1
CPS0
ECF
Bit:
Symbol
Function
CIDL
Counter Idle control: CIDL = 0 programs the PCA Counter to continue functioning during idle Mode. CIDL = 1 programs
it to be gated off during idle.
WDTE
Watchdog Timer Enable: WDTE = 0 disables Watchdog Timer function on PCA Module 4. WDTE = 1 enables it.
–
Not implemented, reserved for future use.*
CPS1
PCA Count Pulse Select bit 1.
CPS0
PCA Count Pulse Select bit 0.
CPS1
CPS0
Selected PCA Input**
0
Internal clock, fOSC/6 in 6-clock mode (fOSC/12 in 12-clock mode)
0
1
Internal clock, fOSC/2 in 6-clock mode (fOSC/4 in 12-clock mode)
1
0
2
Timer 0 overflow
1
3
External clock at ECI/P1.2 pin
(max. rate = fOSC/4 in 6-clock mode, fOCS/8 in 12-clock mode)
ECF
PCA Enable Counter Overflow interrupt: ECF = 1 enables CF bit in CCON to generate an interrupt. ECF = 0 disables
that function of CF.
NOTE:
*
User software should not write 1s to reserved bits. These bits may be used in future 8051 family products to invoke new features. In that case, the reset or inactive
value of the new bit will be 0, and its active value will be 1. The value read from a reserved bit is indeterminate.
** fOSC = oscillator frequency
SU01318
7
6
5
432
1
0
Figure 22. CMOD: PCA Counter Mode Register
CCON Address = D8H
Reset Value = 00X0 0000B
CF
CR
–
CCF4
CCF3
CCF2
CCF1
CCF0
Bit Addressable
Bit:
Symbol
Function
CF
PCA Counter Overflow flag. Set by hardware when the counter rolls over. CF flags an interrupt if bit ECF in CMOD is
set. CF may be set by either hardware or software but can only be cleared by software.
CR
PCA Counter Run control bit. Set by software to turn the PCA counter on. Must be cleared by software to turn the PCA
counter off.
–
Not implemented, reserved for future use*.
CCF4
PCA Module 4 interrupt flag. Set by hardware when a match or capture occurs. Must be cleared by software.
CCF3
PCA Module 3 interrupt flag. Set by hardware when a match or capture occurs. Must be cleared by software.
CCF2
PCA Module 2 interrupt flag. Set by hardware when a match or capture occurs. Must be cleared by software.
CCF1
PCA Module 1 interrupt flag. Set by hardware when a match or capture occurs. Must be cleared by software.
CCF0
PCA Module 0 interrupt flag. Set by hardware when a match or capture occurs. Must be cleared by software.
NOTE:
*
User software should not write 1s to reserved bits. These bits may be used in future 8051 family products to invoke new features. In that case, the reset or inactive
value of the new bit will be 0, and its active value will be 1. The value read from a reserved bit is indeterminate.
SU01319
76
5
4
3
210
Figure 23. CCON: PCA Counter Control Register
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