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| 型号： | P87C766 |
| 厂商： | NXP Semiconductors N.V. |
| 英文描述： | Microcontrollers for PAL/SECAM TV with OSD and VST |
| 中文描述： | 微控制器对于PAL / SECAM电视的OSD和伟仕 |
| 文件页数： | 31/92页 |
| 文件大小： | 382K |
| 代理商： | P87C766 |
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1999 Mar 10
31
Philips Semiconductors
Product specification
Microcontrollers for PAL/SECAM TV
with OSD and VST
P8xCx66 family
13 RESET CIRCUITRY
To initialize the P8xCx66 a reset is performed by one of
3 methods:
Via the RESET pin
Via a Power-on reset
Via the Watchdog timer.
A reset leaves the internal registers as shown in Table 35.
The reset input of the P8xCx66 is the RESET pin. A
Schmitt trigger input qualifies the input for noise rejection.
The output of the Schmitt trigger is sampled by the reset
circuitry every machine cycle. A reset is accomplished by
holding the RESET pin HIGH for at least two machine
cycles (24 oscillator periods), while the oscillator is
running. The CPU responds by generating an internal
reset. Port pins adopt their reset state immediately after
RESET goes HIGH.
The external reset is asynchronous to the internal clock.
The RESET pin is sampled during state 5, phase 2 of
every machine cycle. After a HIGH is detected at the
RESET pin, an internal reset is repeated until RESET goes
LOW.
The internal RAM is not affected by reset. When V
DD
is
switched on the RAM contents are indeterminate.
13.1
Reset operation for the OSD SFRs
There are 12 OSD Special Function Registers: OSAT,
OSDT, OSAD, OSCON, OSCON2, OSORGV, OSORGH,
OSDDEF, OSSTART, HDEL, OSFBD and OSPLL.
The OSD SFRs are only updated when VSYNC and
HSYNC are present. If these signals are not present during
a reset operation then the OSD SFRs will retain their
values held after a Power-on reset.
In existing television systems HSYNC and VSYNC are
often generated by a dedicated IC, consequently during
start-up these signals may not be present. In this situation,
it is mandatory to initialize all the OSD registers before
entering the application.
13.2
Power-on reset
The P8xCx66 contains on-chip circuitry which switches the
port to the customer defined logic level as soon as V
DD
exceeds 3.9 V. As soon as the minimum supply voltage is
reached, the oscillator will start-up. However, to ensure
that the oscillator is stable before the controller starts, the
reset is extended internally for 2048 oscillator periods.
A hysteresis of approximately 500 mV at a typical
power-on switching level of 3.9 V will ensure correct
operation.
An automatic reset can be obtained at power-on by
connecting the RESET pin to V
DD
via a 10
μ
F capacitor.
At power-on, the voltage on the RESET pin is equal to V
DD
minus the capacitor voltage, and decreases from V
DD
as
the capacitor discharges through the internal resistor
R
RESET
to ground. The larger the capacitor, the more
slowly V
RESET
decreases. V
RESET
must remain above the
lower threshold of the Schmitt trigger input long enough to
effect a complete reset. The time required is
2048 oscillator cycles plus 2 machine cycles.
Fig.16 Reset configuration at RESET pin.
handbook, halfpage
MGL293
SCHMITT
TRIGGER
RESET
CIRCUITRY
RESET
Fig.17 Recommended Power-on reset circuity.
handbook, halfpage
MGL291
P8xCx66
10
μ
F
RRESET
RESET
VDD
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