参数资料
型号: P87LPC767FD,512
厂商: NXP Semiconductors
文件页数: 27/61页
文件大小: 0K
描述: IC 80C51 MCU 4K OTP 20-SOIC
产品培训模块: Migrating from 8/16-Bit MCUs to 32-Bit ARMs
标准包装: 38
系列: LPC700
核心处理器: 8051
芯体尺寸: 8-位
速度: 20MHz
连通性: I²C,UART/USART
外围设备: 欠压检测/复位,LED,POR,WDT
输入/输出数: 18
程序存储器容量: 4KB(4K x 8)
程序存储器类型: OTP
RAM 容量: 128 x 8
电压 - 电源 (Vcc/Vdd): 2.7 V ~ 6 V
数据转换器: A/D 4x8b
振荡器型: 内部
工作温度: -40°C ~ 85°C
封装/外壳: 20-SOIC(0.295",7.50mm 宽)
包装: 管件
产品目录页面: 706 (CN2011-ZH PDF)
其它名称: 568-3216-5
935267191512
P87LPC767FD
Philips Semiconductors
Product data
P87LPC767
Low power, low price, low pin count (20 pin)
microcontroller with 4-kbyte OTP and 8-bit A/D converter
2002 Mar 25
30
Low Voltage EPROM Operation
The EPROM array contains some analog circuits that are not
required when VDD is less than 4 V, but are required for a VDD
greater than 4 V. The LPEP bit (AUXR.4), when set by software, will
power down these analog circuits resulting in a reduced supply
current. LPEP is cleared only by power-on reset, so it may be set
ONLY for applications that always operate with VDD less than 4 V.
Reset
The P87LPC767 has an integrated power-on reset circuit which
always provides a reset when power is initially applied to the device.
It is recommended to use the internal reset whenever possible to
save external components and to be able to use pin P1.5 as a
general-purpose input pin.
The P87LPC767 can additionally be configured to use P1.5 as an
external active-low reset pin RST by programming the RPD bit in the
User Configuration Register UCFG1 to 0. The internal reset is still
active on power-up of the device. While the signal on the RST pin is
low, the P87LPC767 is held in reset until the signal goes high.
The watchdog timer on the P87LPC767 can act as an oscillator fail
detect because it uses an independent, fully on-chip oscillator.
UCFG1 is described in the System Configuration Bytes section of
this datasheet.
SU01359
87LPC767
P1.5
Pin is used as
digital input pin
Internal power-on
Reset active
UCFG1.RPD = 1 (default)
RST
Pin is used as
active-low reset pin
Internal power-on
Reset active
UCFG1.RPD = 0
Figure 22. Using pin P1.5 as general purpose input pin or as low-active reset pin
SU01170
CHIP RESET
CPU
CLOCK
Q
RESET
TIMING
RPD (UCFG1.6)
WDT
MODULE
SOFTWARE RESET
SRST (AUXR1.3)
POWER MONITOR
RESET
RST/VPP PIN
WDTE (UCFG1.7)
S
R
Figure 23. Block Diagram Showing Reset Sources
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