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参数资料
| 型号： | P89C538NBBB |
| 厂商： | NXP SEMICONDUCTORS |
| 元件分类： | 微控制器/微处理器 |
| 英文描述： | CMOS single-chip 8-bit microcontrollers with FLASH program memory |
| 中文描述： | 8-BIT, FLASH, 33 MHz, MICROCONTROLLER, PQFP44 |
| 封装： | 10 X 10 X 1.75 MM, PLASTIC, SOT-307-2, QFP-44 |
| 文件页数： | 18/35页 |
| 文件大小： | 221K |
| 代理商： | P89C538NBBB |
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Philips Semiconductors
Preliminary specification
89C535/89C536/89C538
CMOS single-chip 8-bit microcontrollers
with FLASH program memory
1997 Jun 05
18
AC ELECTRICAL CHARACTERISTICS
T
amb
= 0
°
C to +70
°
C, V
CC
= 5V
±
10%, V
SS
= 0V
1, 2, 3
VARIABLE CLOCK
MIN
3.5
33MHz CLOCK
MIN
SYMBOL
1/t
CLCL
FIGURE
9
PARAMETER
MAX
33
MAX
UNIT
Oscillator frequency
Speed versions : N (33MHz)
3.5
33
MHz
t
LHLL
t
AVLL
t
LLAX
t
LLIV
t
LLPL
t
PLPH
t
PLIV
t
PXIX
t
PXIZ
t
AVIV
t
PLAZ
Data Memory
t
RLRH
t
WLWH
t
RLDV
t
RHDX
t
RHDZ
t
LLDV
t
AVDV
t
LLWL
t
AVWL
t
QVWX
t
WHQX
t
QVWH
t
RLAZ
t
WHLH
External Clock
t
CHCX
t
CLCX
t
CLCH
t
CHCL
Shift Register
t
XLXL
t
QVXH
t
XHQX
t
XHDX
t
XHDV
NOTES:
1. Parameters are valid over operating temperature range unless otherwise specified.
2. Load capacitance for port 0, ALE, and PSEN = 100pF, load capacitance for all other outputs = 80pF.
3. Interfacing the microcontroller to devices with float times up to 45ns is permitted. This limited bus contention will not cause damage to Port 0
drivers.
9
9
9
9
9
9
9
9
9
9
9
ALE pulse width
Address valid to ALE low
Address hold after ALE low
ALE low to valid instruction in
ALE low to PSEN low
PSEN pulse width
PSEN low to valid instruction in
Input instruction hold after PSEN
Input instruction float after PSEN
Address to valid instruction in
PSEN low to address float
2t
CLCL
–40
t
CLCL
–25
t
CLCL
–25
21
5
5
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
4t
CLCL
–65
55
t
CLCL
–25
3t
CLCL
–45
5
45
3t
CLCL
–60
30
0
0
t
CLCL
–25
5t
CLCL
–80
10
5
70
10
10, 11
10, 11
10, 11
10, 11
10, 11
10, 11
10, 11
10, 11
10, 11
10, 11
10, 11
11
10, 11
10, 11
RD pulse width
WR pulse width
RD low to valid data in
Data hold after RD
Data float after RD
ALE low to valid data in
Address to valid data in
ALE low to RD or WR low
Address valid to WR low or RD low
Data valid to WR transition
Data hold after WR
Data valid to WR high
RD low to address float
RD or WR high to ALE high
6t
CLCL
–100
6t
CLCL
–100
82
82
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
5t
CLCL
–90
60
0
0
2t
CLCL
–28
8t
CLCL
–150
9t
CLCL
–165
3t
CLCL
+50
32
90
105
140
3t
CLCL
–50
4t
CLCL
–75
t
CLCL
–30
t
CLCL
–25
7t
CLCL
–130
40
45
0
5
80
0
0
55
t
CLCL
–25
t
CLCL
+25
5
13
13
13
13
High time
Low time
Rise time
Fall time
17
17
t
CLCL
–t
CLCX
t
CLCL
–t
CHCX
5
5
ns
ns
ns
ns
12
12
12
12
12
Serial port clock cycle time
Output data setup to clock rising edge
Output data hold after clock rising edge
Input data hold after clock rising edge
Clock rising edge to input data valid
12t
CLCL
10t
CLCL
–133
2t
CLCL
–80
0
360
167
50
0
ns
ns
ns
ns
ns
10t
CLCL
–133
167
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