参数资料
型号: P89C61X2
厂商: NXP Semiconductors N.V.
元件分类: 8位微控制器
英文描述: 80C51 8-bit Flash microcontroller family
中文描述: 80C51的8位闪存微控制器系列
文件页数: 13/56页
文件大小: 342K
代理商: P89C61X2
Philips Semiconductors
Product data
P89C60X2/61X2
80C51 8-bit Flash microcontroller family
64KB Flash, 512B/1024B RAM
2003 Sep 11
13
Table 1.
CLOCK MODE CONFIG BIT (FX2)
erased
erased
programmed
X2 bit in CKCON
0
1
x
DESCRIPTION
12-clock mode (default)
6-clock mode
6-clock mode
NOTE:
1. Default clock mode after ChipErase is set to 12-clock.
FFFF
C000
8000
4000
2000
0000
PROGRAM
ADDRESS
BOOT ROM
(1 kB)
SU01673
P89C60X2
P89C61X2
BLOCK 1
BLOCK 0
BLOCK 3
BLOCK 2
BLOCK 5
BLOCK 4
BLOCK 7
BLOCK 6
BLOCK 9
BLOCK 8
BLOCK 11
BLOCK 10
BLOCK 13
BLOCK 12
BLOCK 15
BLOCK 14
Each block is
4 kbytes in size
Figure 1. Flash Memory Configuration
Power-On Reset Code Execution
The P89C60X2/61X2 contains a special Flash register, the STATUS
BYTE. At the falling edge of reset, the P89C60X2/61X2 examines
the contents of the Status Byte. If the Status Byte is set to zero,
power-up execution starts at location 0000H, which is the normal
start address of the user’s application code. When the Status Byte is
set to a value other than zero, the factory masked-ROM ISP boot
loader is invoked. The factory default for the Status Byte is FFh.
Once set to 00h, the Status Byte can only be changed back to FFh
by a full-chip erase operation when using ISP.
Hardware Activation of the Boot Loader
The boot loader can also be executed by holding PSEN LOW,
EA greater than V
IH
(such as +5 V), and ALE HIGH (or not connected)
at the falling edge of RESET. This is the same effect as having a
non-zero status byte. This allows an application to be built that will
normally execute the end user’s code but can be manually forced
into ISP operation.
After programming the Flash, the status byte should be programmed
to zero in order to allow execution of the user’s application code
beginning at address 0000H.
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