参数资料
型号: P89LPC9161FDH,129
厂商: NXP Semiconductors
文件页数: 13/27页
文件大小: 0K
描述: IC 80C51 MCU FLASH 2KB 16TSSOP
标准包装: 96
系列: LPC900
核心处理器: 8051
芯体尺寸: 8-位
速度: 18MHz
连通性: I²C,SPI,UART/USART
外围设备: 欠压检测/复位,POR,PWM,WDT
输入/输出数: 14
程序存储器容量: 2KB(2K x 8)
程序存储器类型: 闪存
RAM 容量: 256 x 8
电压 - 电源 (Vcc/Vdd): 2.4 V ~ 3.6 V
数据转换器: A/D 4x8b; D/A 1x8b
振荡器型: 内部
工作温度: -40°C ~ 85°C
封装/外壳: 16-TSSOP(0.173",4.40mm 宽)
包装: 管件
其它名称: 935290261129
PIC18F87J72 FAMILY
DS39979A-page 78
Preliminary
2010 Microchip Technology Inc.
FIGURE 7-2:
TABLE WRITE OPERATION
7.2
Control Registers
Several control registers are used in conjunction with
the TBLRD and TBLWT instructions. These include the:
EECON1 register
EECON2 register
TABLAT register
TBLPTR registers
7.2.1
EECON1 AND EECON2 REGISTERS
The EECON1 register (Register 7-1) is the control
register for memory accesses. The EECON2 register is
not a physical register; it is used exclusively in the
memory write and erase sequences. Reading
EECON2 will read all ‘0’s.
The WPROG bit, when set, allows the user to program
a single word (two bytes) upon the execution of the WR
command. If this bit is cleared, the WR command
programs a block of 64 bytes.
The FREE bit, when set, will allow a program memory
erase operation. When FREE is set, the erase
operation is initiated on the next WR command. When
FREE is clear, only writes are enabled.
The WREN bit, when set, will allow a write operation.
On power-up, the WREN bit is clear. The WRERR bit is
set in hardware when the WR bit is set and cleared
when the internal programming timer expires and the
write operation is complete.
The WR control bit initiates write operations. The bit
cannot be cleared, only set, in software. It is cleared in
hardware at the completion of the write operation.
Table Pointer(1)
Table Latch (8-bit)
TBLPTRH
TBLPTRL
TABLAT
Program Memory
(TBLPTR)
TBLPTRU
Instruction: TBLWT*
Note 1:
Table Pointer actually points to one of 64 holding registers, the address of which is determined by
TBLPTRL<5:0>. The process for physically writing data to the program memory array is discussed in
Holding Registers
Program Memory
Note:
During normal operation, the WRERR is
read as ‘1’. This can indicate that a write
operation was prematurely terminated by
a Reset, or a write operation was
attempted improperly.
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