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参数资料
| 型号： | P89LPC9171FDH,129 |
| 厂商： | NXP Semiconductors |
| 文件页数： | 16/27页 |
| 文件大小： | 0K |
| 描述： | IC 80C51 MCU FLASH 2KB 16TSSOP |
| 标准包装： | 96 |
| 系列： | LPC900 |
| 核心处理器： | 8051 |
| 芯体尺寸： | 8-位 |
| 速度： | 18MHz |
| 连通性： | I²C，UART/USART |
| 外围设备： | 欠压检测/复位，POR，PWM，WDT |
| 输入/输出数： | 14 |
| 程序存储器容量： | 2KB（2K x 8） |
| 程序存储器类型： | 闪存 |
| RAM 容量： | 256 x 8 |
| 电压 - 电源 (Vcc/Vdd)： | 2.4 V ~ 3.6 V |
| 数据转换器： | A/D 4x8b; D/A 1x8b |
| 振荡器型： | 内部 |
| 工作温度： | -40°C ~ 85°C |
| 封装/外壳： | 16-TSSOP（0.173"，4.40mm 宽） |
| 包装： | 管件 |
| 其它名称： | 935290262129 |
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PIC18F87J72 FAMILY
DS39979A-page 80
Preliminary
2010 Microchip Technology Inc.
7.2.2
TABLE LATCH REGISTER (TABLAT)
The Table Latch (TABLAT) is an 8-bit register mapped
into the SFR space. The Table Latch register is used to
hold 8-bit data during data transfers between program
memory and data RAM.
7.2.3
TABLE POINTER REGISTER
(TBLPTR)
The Table Pointer (TBLPTR) register addresses a byte
within the program memory. The TBLPTR is comprised
of three SFR registers: Table Pointer Upper Byte, Table
Pointer High Byte and Table Pointer Low Byte
(TBLPTRU:TBLPTRH:TBLPTRL). These three regis-
ters join to form a 22-bit wide pointer. The low-order
21 bits allow the device to address up to 2 Mbytes of
program memory space. The 22nd bit allows access to
the device ID, the user ID and the Configuration bits.
The Table Pointer register, TBLPTR, is used by the
TBLRD and TBLWT instructions. These instructions can
update the TBLPTR in one of four ways based on the
table operation. These operations are shown in
Table 7-1. These operations on the TBLPTR only affect
the low-order 21 bits.
7.2.4
TABLE POINTER BOUNDARIES
TBLPTR is used in reads, writes and erases of the
Flash program memory.
When a TBLRD is executed, all 22 bits of the TBLPTR
determine which byte is read from program memory
into TABLAT.
When a TBLWT is executed, the seven LSbs of the
Table Pointer register (TBLPTR<6:0>) determine which
of the 64 program memory holding registers is written
to. When the timed write to program memory begins
(via the WR bit), the 12 MSbs of the TBLPTR
(TBLPTR<21:10>) determine which program memory
block of 1,024 bytes is written to. For more detail, see
When an erase of program memory is executed, the
12 MSbs of the Table Pointer register point to the
1,024-byte block that will be erased. The Least
Significant bits are ignored.
Figure 7-3 describes the relevant boundaries of
TBLPTR based on Flash program memory operations.
TABLE 7-1:
TABLE POINTER OPERATIONS WITH TBLRD AND TBLWT INSTRUCTIONS
FIGURE 7-3:
TABLE POINTER BOUNDARIES BASED ON OPERATION
Example
Operation on Table Pointer
TBLRD*
TBLWT*
TBLPTR is not modified
TBLRD*+
TBLWT*+
TBLPTR is incremented after the read/write
TBLRD*-
TBLWT*-
TBLPTR is decremented after the read/write
TBLRD+*
TBLWT+*
TBLPTR is incremented before the read/write
21
16
15
87
0
ERASE: TBLPTR<20:10>
TABLE WRITE: TBLPTR<20:6>
TABLE READ: TBLPTR<21:0>
TBLPTRL
TBLPTRH
TBLPTRU
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相关代理商/技术参数 |
参数描述 |
|---|---|
| P89LPC917FDH | 制造商:NXP Semiconductors 功能描述:MCU 8BIT 80C51 2K FLASH TSSOP16 制造商:NXP Semiconductors 功能描述:MCU 8BIT 80C51 2K FLASH, TSSOP16 |
| P89LPC917FDH,129 | 功能描述:8位微控制器 -MCU 80C51 2K FL 256B RAM RoHS:否 制造商:Silicon Labs 核心:8051 处理器系列:C8051F39x 数据总线宽度:8 bit 最大时钟频率:50 MHz 程序存储器大小:16 KB 数据 RAM 大小:1 KB 片上 ADC:Yes 工作电源电压:1.8 V to 3.6 V 工作温度范围:- 40 C to + 105 C 封装 / 箱体:QFN-20 安装风格:SMD/SMT |
| P89LPC917FDH129 | 制造商:NXP Semiconductors 功能描述:IC 8BIT MCU 80C51 18MHZ TSSOP-16 |
| P89LPC917FDH-S | 制造商:NXP Semiconductors 功能描述:MCU 8-bit P89 80C51 CISC 2KB Flash 2.5V/3.3V 16-Pin TSSOP |
| P89LPC920 | 制造商:PHILIPS 制造商全称:NXP Semiconductors 功能描述:8-bit microcontrollers with two-clock 80C51 core 2 kB/4 kB/8 kB 3 V low-power Flash with 256-byte data RAM |
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