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参数资料
| 型号： | P89LPC921FN,112 |
| 厂商： | NXP Semiconductors |
| 文件页数： | 27/46页 |
| 文件大小： | 0K |
| 描述： | IC 80C51 MCU FLASH 4K 20-DIP |
| 产品培训模块： | Migrating from 8/16-Bit MCUs to 32-Bit ARMs |
| 标准包装： | 18 |
| 系列： | LPC900 |
| 核心处理器： | 8051 |
| 芯体尺寸： | 8-位 |
| 速度： | 18MHz |
| 连通性： | I²C，UART/USART |
| 外围设备： | 欠压检测/复位，LED，POR，PWM，WDT |
| 输入/输出数： | 18 |
| 程序存储器容量： | 4KB（4K x 8） |
| 程序存储器类型： | 闪存 |
| RAM 容量： | 256 x 8 |
| 电压 - 电源 (Vcc/Vdd)： | 2.4 V ~ 3.6 V |
| 振荡器型： | 内部 |
| 工作温度： | -40°C ~ 85°C |
| 封装/外壳： | 20-DIP（0.300"，7.62mm） |
| 包装： | 管件 |
| 产品目录页面： | 706 (CN2011-ZH PDF) |
| 配用： | 622-1014-ND - BOARD FOR LPC9XX TSSOP 622-1008-ND - BOARD FOR LPC9103 10-HVSON 622-1006-ND - SOCKET ADAPTER BOARD 568-4000-ND - DEMO BOARD SPI/I2C TO DUAL UART 568-3510-ND - DEMO BOARD SPI/I2C TO UART 622-1002-ND - USB IN-CIRCUIT PROG LPC9XX 568-1759-ND - EMULATOR DEBUGGER/PROGRMMR LPC9X |
| 其它名称： | 568-2248-5 935280399112 P89LPC921FN |
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Philips Semiconductors
P89LPC920/921/922/9221
8-bit microcontrollers with two-clock 80C51 core
Product data
Rev. 08 — 15 December 2004
33 of 46
9397 750 14469
Koninklijke Philips Electronics N.V. 2004. All rights reserved.
Flash programming and erasing: There are three methods of erasing or
programming of the Flash memory that may be used. First, the Flash may be
programmed or erased in the end-user application by calling low-level routines
through a common entry point. Second, the on-chip ISP boot loader may be invoked.
This ISP boot loader will, in turn, call low-level routines through the same common
entry point that can be used by the end-user application. Third, the Flash may be
programmed or erased using the parallel method by using a commercially available
EPROM programmer which supports this device. This device does not provide for
direct verication of code memory contents. Instead this device provides a 32-bit
CRC result on either a sector or the entire 2 kB/4 kB/8 kB of user code space.
Boot ROM: When the microcontroller programs its own Flash memory, all of the
low-level details are handled by code that is contained in a Boot ROM that is separate
from the Flash memory. A user program simply calls the common entry point in the
Boot ROM with appropriate parameters to accomplish the desired operation. The
Boot ROM include operations such as erase sector, erase page, program page, CRC,
program security bit, etc. The Boot ROM occupies the program memory space at the
top of the address space from FF00H to FEFFH, thereby not conicting with the user
program memory space.
Power-on reset code execution: The P89LPC920/921/922/9221 contains two
special Flash elements: the Boot Vector and the Boot Status Bit. Following reset, the
P89LPC920/921/922/9221 examines the contents of the Boot Status Bit. If the Boot
Status Bit is set to zero, power-up execution starts at location 0000H, which is the
normal start address of the user’s application code. When the Boot Status Bit is set to
a one, the contents of the Boot Vector is used as the high byte of the execution
address and the low byte is set to 00H. The factory default setting is 1FH for the
P89LPC9221 and P89LPC922, and corresponds to the address 1F00H for the default
ISP boot loader. The factory default setting is 0FH for the P89LPC921 and
corresponds to the address 0F00H for the default ISP boot loader. The factory default
setting for the LPC920 is 07H and corresponds to the address 0700H. This boot
loader is pre-programmed at the factory into this address space and can be erased
by the user. Users who wish to use this loader should take precautions to avoid
erasing the 1 kB sector from 1C00H to 1FFFH in the P89LPC922/9221 or the
1 kB sector from 0C00H to 0FFFH in the P89LPC921, or the 1 kB sector from
0400H to 07FFH in the P89LPC920. Instead, the page erase function can be
used to erase the eight 64-byte pages which comprise the lower 512 bytes of
the sector. A custom boot loader can be written with the Boot Vector set to the
custom boot loader, if desired.
Hardware activation of the boot loader: The boot loader can also be executed by
forcing the device into ISP mode during a power-on sequence (see the
P89LPC920/921/922/9221 User’s Manual for specic information). This has the same
effect as having a non-zero Boot Status Bit. This allows an application to be built that
will normally execute user code but can be manually forced into ISP operation. If the
factory default setting for the Boot Vector is changed, it will no longer point to the
factory pre-programmed ISP boot loader code. If this happens, the only way it is
possible to change the contents of the Boot Vector is through the parallel
programming method, provided that the end user application does not contain a
customized loader that provides for erasing and reprogramming of the Boot Vector
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相关代理商/技术参数 |
参数描述 |
|---|---|
| P89LPC922 | 制造商:PHILIPS 制造商全称:NXP Semiconductors 功能描述:8-bit microcontrollers with two-clock 80C51 core 2 kB/4 kB/8 kB 3 V low-power Flash with 256-byte data RAM |
| P89LPC9221FDH,512 | 功能描述:8位微控制器 -MCU 80C51 8K FL 256B RAM RoHS:否 制造商:Silicon Labs 核心:8051 处理器系列:C8051F39x 数据总线宽度:8 bit 最大时钟频率:50 MHz 程序存储器大小:16 KB 数据 RAM 大小:1 KB 片上 ADC:Yes 工作电源电压:1.8 V to 3.6 V 工作温度范围:- 40 C to + 105 C 封装 / 箱体:QFN-20 安装风格:SMD/SMT |
| P89LPC9221FDH,518 | 功能描述:8位微控制器 -MCU 8B MCU 80C51 2/4/8KB 3V FL 256B RAM RoHS:否 制造商:Silicon Labs 核心:8051 处理器系列:C8051F39x 数据总线宽度:8 bit 最大时钟频率:50 MHz 程序存储器大小:16 KB 数据 RAM 大小:1 KB 片上 ADC:Yes 工作电源电压:1.8 V to 3.6 V 工作温度范围:- 40 C to + 105 C 封装 / 箱体:QFN-20 安装风格:SMD/SMT |
| P89LPC9221FN | 功能描述:8位微控制器 -MCU 80C51 8K FL 256B RAM RoHS:否 制造商:Silicon Labs 核心:8051 处理器系列:C8051F39x 数据总线宽度:8 bit 最大时钟频率:50 MHz 程序存储器大小:16 KB 数据 RAM 大小:1 KB 片上 ADC:Yes 工作电源电压:1.8 V to 3.6 V 工作温度范围:- 40 C to + 105 C 封装 / 箱体:QFN-20 安装风格:SMD/SMT |
| P89LPC9221FN,112 | 功能描述:8位微控制器 -MCU 8K FL/256B RAM/I2C/UART/DIP20 RoHS:否 制造商:Silicon Labs 核心:8051 处理器系列:C8051F39x 数据总线宽度:8 bit 最大时钟频率:50 MHz 程序存储器大小:16 KB 数据 RAM 大小:1 KB 片上 ADC:Yes 工作电源电压:1.8 V to 3.6 V 工作温度范围:- 40 C to + 105 C 封装 / 箱体:QFN-20 安装风格:SMD/SMT |
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