参数资料
型号: P89LPC9321FDH,512
厂商: NXP Semiconductors
文件页数: 39/71页
文件大小: 0K
描述: IC 80C51 MCU 8KB FLASH 28TSSOP
标准包装: 51
系列: LPC900
核心处理器: 8051
芯体尺寸: 8-位
速度: 18MHz
连通性: I²C,SPI,UART/USART
外围设备: 欠压检测/复位,POR,PWM,WDT
输入/输出数: 26
程序存储器容量: 8KB(8K x 8)
程序存储器类型: 闪存
EEPROM 大小: 512 x 8
RAM 容量: 768 x 8
电压 - 电源 (Vcc/Vdd): 2.4 V ~ 3.6 V
振荡器型: 内部
工作温度: -40°C ~ 85°C
封装/外壳: 28-TSSOP(0.173",4.40mm 宽)
包装: 管件
P89LPC9321
All information provided in this document is subject to legal disclaimers.
NXP B.V. 2010. All rights reserved.
Product data sheet
Rev. 2 — 16 November 2010
44 of 71
NXP Semiconductors
P89LPC9321
8-bit microcontroller with accelerated two-clock 80C51 core
7.27 KBI
The Keypad Interrupt function (KBI) is intended primarily to allow a single interrupt to be
generated when Port 0 is equal to or not equal to a certain pattern. This function can be
used for bus address recognition or keypad recognition. The user can configure the port
via SFRs for different tasks.
The Keypad Interrupt Mask Register (KBMASK) is used to define which input pins
connected to Port 0 can trigger the interrupt. The Keypad Pattern Register (KBPATN) is
used to define a pattern that is compared to the value of Port 0. The Keypad Interrupt Flag
(KBIF) in the Keypad Interrupt Control Register (KBCON) is set when the condition is
matched while the Keypad Interrupt function is active. An interrupt will be generated if
enabled. The PATN_SEL bit in the Keypad Interrupt Control Register (KBCON) is used to
define equal or not-equal for the comparison.
In order to use the Keypad Interrupt as an original KBI function like in 87LPC76x series,
the user needs to set KBPATN = 0FFH and PATN_SEL = 1 (not equal), then any key
connected to Port 0 which is enabled by the KBMASK register will cause the hardware to
set KBIF and generate an interrupt if it has been enabled. The interrupt may be used to
wake-up the CPU from Idle or Power-down modes. This feature is particularly useful in
handheld, battery-powered systems that need to carefully manage power consumption
yet also need to be convenient to use.
In order to set the flag and cause an interrupt, the pattern on Port 0 must be held longer
than six CCLKs.
7.28 Watchdog timer
The watchdog timer causes a system reset when it underflows as a result of a failure to
feed the timer prior to the timer reaching its terminal count. It consists of a programmable
12-bit prescaler, and an 8-bit down counter. The down counter is decremented by a tap
taken from the prescaler. The clock source for the prescaler can be the PCLK, the nominal
400 kHz watchdog oscillator or low speed crystal oscillator. The watchdog timer can only
be reset by a power-on reset. When the watchdog feature is disabled, it can be used as
an interval timer and may generate an interrupt. Figure 20 shows the watchdog timer in
Watchdog mode. Feeding the watchdog requires a two-byte sequence. If PCLK is
selected as the watchdog clock and the CPU is powered down, the watchdog is disabled.
The watchdog timer has a time-out period that ranges from a few
μs to a few seconds.
Please refer to the P89LPC9321 User manual for more details.
相关PDF资料
PDF描述
P89LPC9321FDH,518 IC 80C51 MCU FLASH 8K 28-TSSOP
VI-BN3-IX-F4 CONVERTER MOD DC/DC 24V 75W
VI-BN3-IX-F3 CONVERTER MOD DC/DC 24V 75W
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