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| 型号： | P89LPC9331FDH |
| 厂商： | NXP SEMICONDUCTORS |
| 元件分类： | 微控制器/微处理器 |
| 英文描述： | 8-bit microcontroller with accelerated two-clock 80C51 core, 4 kB-8 kB-16 kB 3 V byte-erasable flash with 8-bit ADCs |
| 中文描述： | 8-BIT, FLASH, 18 MHz, MICROCONTROLLER, PDSO28 |
| 封装： | 4.40 MM, PLASTIC, MO-153, SOT361-1, TSSOP-28 |
| 文件页数： | 26/94页 |
| 文件大小： | 629K |
| 代理商： | P89LPC9331FDH |
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P89LPC9331_9341_9351_9361
All information provided in this document is subject to legal disclaimers.
NXP B.V. 2011. All rights reserved.
Product data sheet
Rev. 5 — 10 January 2011
32 of 94
NXP Semiconductors
P89LPC9331/9341/9351/9361
8-bit microcontroller with accelerated two-clock 80C51 core
7.10 CCLK wake-up delay
The P89LPC9331/9341/9351/9361 has an internal wake-up timer that delays the clock
until it stabilizes depending on the clock source used. If the clock source is any of the
three crystal selections (low, medium and high frequencies) the delay is 1024 OSCCLK
cycles plus 60
μsto100 μs. If the clock source is the internal RC oscillator, the delay is
200
μs to 300 μs. If the clock source is watchdog oscillator or external clock, the delay is
32 OSCCLK cycles.
7.11 CCLK modification: DIVM register
The OSCCLK frequency can be divided down up to 510 times by configuring a dividing
register, DIVM, to generate CCLK. This feature makes it possible to temporarily run the
CPU at a lower rate, reducing power consumption. By dividing the clock, the CPU can
retain the ability to respond to events that would not exit Idle mode by executing its normal
program at a lower rate. This can also allow bypassing the oscillator start-up time in cases
where Power-down mode would otherwise be used. The value of DIVM may be changed
by the program at any time without interrupting code execution.
7.12 Low power select
The P89LPC9331/9341/9351/9361 is designed to run at 18 MHz (CCLK) maximum.
However, if CCLK is 8 MHz or slower, the CLKLP SFR bit (AUXR1.7) can be set to logic 1
to lower the power consumption further. On any reset, CLKLP is logic 0 allowing highest
performance access. This bit can then be set in software if CCLK is running at 8 MHz or
slower.
Fig 7.
Block diagram of oscillator control
÷2
002aad559
RTC
ADC1
ADC0
CPU
WDT
DIVM
CCLK
UART
OSCCLK
I2C-BUS
PCLK
TIMER 0 AND
TIMER 1
HIGH FREQUENCY
MEDIUM FREQUENCY
LOW FREQUENCY
XTAL1
XTAL2
RC OSCILLATOR
WITH CLOCK DOUBLER
WATCHDOG
OSCILLATOR
(7.3728 MHz/14.7456 MHz
± 1 %)
PCLK
RCCLK
SPI
CCU
(P89LPC9351/9361)
32
× PLL
(400 kHz
± 5 %)
相关PDF资料 |
PDF描述 |
|---|---|
| P89LPC9331HDH | 8-bit microcontroller with accelerated two-clock 80C51 core, 4 kB-8 kB-16 kB 3 V byte-erasable flash with 8-bit ADCs |
| P89LPC9341FDH | 8-bit microcontroller with accelerated two-clock 80C51 core, 4 kB-8 kB-16 kB 3 V byte-erasable flash with 8-bit ADCs |
| P89LPC9351FDH | 8-bit microcontroller with accelerated two-clock 80C51 core, 4 kB-8 kB-16 kB 3 V byte-erasable flash with 8-bit ADCs |
| P89LPC9361FDH | 8-bit microcontroller with accelerated two-clock 80C51 core, 4 kB-8 kB-16 kB 3 V byte-erasable flash with 8-bit ADCs |
| P89LPC933FDH | 8-bit microcontroller with accelerated two-clock 80C51 core 4 kB-8 kB-16 kB 3 V byte-erasable flash with 8-bit ADCs |
相关代理商/技术参数 |
参数描述 |
|---|---|
| P89LPC9331FDH,512 | 功能描述:8位微控制器 -MCU IC 80C51 MCU FLASH 4K RoHS:否 制造商:Silicon Labs 核心:8051 处理器系列:C8051F39x 数据总线宽度:8 bit 最大时钟频率:50 MHz 程序存储器大小:16 KB 数据 RAM 大小:1 KB 片上 ADC:Yes 工作电源电压:1.8 V to 3.6 V 工作温度范围:- 40 C to + 105 C 封装 / 箱体:QFN-20 安装风格:SMD/SMT |
| P89LPC9331FDH512 | 制造商:Rochester Electronics LLC 功能描述: 制造商:NXP 功能描述: 制造商:NXP Semiconductors 功能描述: |
| P89LPC9331HDH | 制造商:PHILIPS 制造商全称:NXP Semiconductors 功能描述:8-bit microcontroller with accelerated two-clock 80C51 core, 4 kB/8 kB/16 kB 3 V byte-erasable flash with 8-bit ADCs |
| P89LPC933FDH | 制造商:NXP Semiconductors 功能描述:MCU 8BIT 80C51 4K FLASH TSSOP28 |
| P89LPC933FDH,529 | 功能描述:8位微控制器 -MCU 80C51 4K FL 256B RAM RoHS:否 制造商:Silicon Labs 核心:8051 处理器系列:C8051F39x 数据总线宽度:8 bit 最大时钟频率:50 MHz 程序存储器大小:16 KB 数据 RAM 大小:1 KB 片上 ADC:Yes 工作电源电压:1.8 V to 3.6 V 工作温度范围:- 40 C to + 105 C 封装 / 箱体:QFN-20 安装风格:SMD/SMT |
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