参数资料
型号: P89LPC9351FA,529
厂商: NXP Semiconductors
文件页数: 44/94页
文件大小: 0K
描述: IC 80C51 MCU FLASH 8K 28-PLCC
标准包装: 37
系列: LPC900
核心处理器: 8051
芯体尺寸: 8-位
速度: 18MHz
连通性: I²C,SPI,UART/USART
外围设备: 欠压检测/复位,POR,PWM,温度传感器,WDT
输入/输出数: 26
程序存储器容量: 8KB(8K x 8)
程序存储器类型: 闪存
EEPROM 大小: 512 x 8
RAM 容量: 768 x 8
电压 - 电源 (Vcc/Vdd): 2.4 V ~ 3.6 V
数据转换器: A/D 8x8b; D/A 2x8b
振荡器型: 内部
工作温度: -40°C ~ 85°C
封装/外壳: 28-PLCC
包装: 管件
配用: 568-1758-ND - BOARD EVAL FOR LPC93X MCU FAMILY
其它名称: 935287627529
P89LPC9331_9341_9351_9361
All information provided in this document is subject to legal disclaimers.
NXP B.V. 2012. All rights reserved.
Product data sheet
Rev. 5.1 — 20 August 2012
49 of 94
NXP Semiconductors
P89LPC9331/9341/9351/9361
8-bit microcontroller with accelerated two-clock 80C51 core
7.25 SPI
The P89LPC9331/9341/9351/9361 provides another high-speed serial communication
interface: the SPI interface. SPI is a full-duplex, high-speed, synchronous communication
bus with two operation modes: Master mode and Slave mode. Up to 3 Mbit/s can be
supported in either Master mode or Slave mode. It has a Transfer Completion Flag and
Write Collision Flag Protection.
The SPI interface has four pins: SPICLK, MOSI, MISO and SS:
SPICLK, MOSI and MISO are typically tied together between two or more SPI
devices. Data flows from master to slave on MOSI (Master Out Slave In) pin and flows
from slave to master on MISO (Master In Slave Out) pin. The SPICLK signal is output
in the Master mode and is input in the Slave mode. If the SPI system is disabled, i.e.,
SPEN (SPCTL.6) = 0 (reset value), these pins are configured for port functions.
SS is the optional slave select pin. In a typical configuration, an SPI master asserts
one of its port pins to select one SPI device as the current slave. An SPI slave device
uses its SS pin to determine whether it is selected.
Typical connections are shown in Figure 17 through Figure 19.
Fig 16. SPI block diagram
002aaa900
CPU clock
DIVIDER
BY 4, 16, 64, 128
SELECT
CLOCK LOGIC
SPI CONTROL REGISTER
READ DATA BUFFER
8-BIT SHIFT REGISTER
SPI CONTROL
SPI STATUS REGISTER
SPR1
SPIF
WCOL
SPR0
SPI clock (master)
PIN
CONTROL
LOGIC
S
M
S
M
S
MISO
P2.3
MOSI
P2.2
SPICLK
P2.5
SS
P2.4
SPI
interrupt
request
internal
data
bus
SSIG
SPEN
MSTR
DORD
MSTR
CPHA
CPOL
SPR1
SPR0
MSTR
SPEN
clock
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