参数资料
型号: P89LPC935
厂商: NXP Semiconductors N.V.
元件分类: 串行ADC
英文描述: 8-bit microcontroller with accelerated two-clock 80C51 core 4 kB/8 kB 3 V byte-erasable Flash with 8-bit A/D converters
中文描述: 8位加速两个微控制器80C51的时钟4 KB的核心/ 8 KB的3伏字节可擦除闪存的8位A / D转换器
文件页数: 17/75页
文件大小: 372K
代理商: P89LPC935
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Special function registers - P89LPC933/934
…continued
* indicates SFRs that are bit addressable.
Name
Description
SFR
addr.
MSB
9
P
R
1
P
P
8
[1]
Unimplemented bits in SFRs (labeled ’-’) are X (unknown) at all times. Unless otherwise specified, ones should not be written to these bits since they may be used for other
purposes in future derivatives. The reset values shown for these bits are logic 0s although they are unknown when read.
[2]
BRGR1 and BRGR0 must only be written if BRGEN in BRGCON SFR is logic 0. If any are written while BRGEN = 1, the result is unpredictable.
[3]
All ports are in input only (high-impedance) state after power-up.
[4]
The RSTSRC register reflects the cause of the P89LPC933/934/935/936 reset. Upon a power-up reset, all reset source flags are cleared except POF and BOF; the power-on reset
value is xx11 0000.
[5]
The only reset source that affects these SFRs is power-on reset.
[6]
On power-on reset, the TRIM SFR is initialized with a factory preprogrammed value. Other resets will not cause initialization of the TRIM register.
[7]
After reset, the value is 1110 01x1, i.e., PRE2 to PRE0 are all logic 1, WDRUN = 1 and WDCLK = 1. WDTOF bit is logic 1 after watchdog reset and is logic 0 after power-on reset.
Other resets will not affect WDTOF.
WDL
WFEED1
WFEED2
Watchdog load
Watchdog feed 1
Watchdog feed 2
C1H
C2H
C3H
FF
1111 1111
Table 5:
Bit functions and addresses
Reset value
Hex
LSB
Binary
相关PDF资料
PDF描述
P89LPC935FA 8-bit microcontroller with accelerated two-clock 80C51 core 4 kB/8 kB 3 V byte-erasable Flash with 8-bit A/D converters
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P89LPC938 8-bit microcontroller with accelerated two-clock 80C51 core 8 kB 3 V byte-erasable Flash with 10-bit A/D converter
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