- 您现在的位置：买卖IC网 > PDF目录3861 > P89V51RB2FA,529 (NXP Semiconductors)IC 80C51 MCU FLASH 16K 44-PLCC PDF资料下载
参数资料
| 型号： | P89V51RB2FA,529 |
| 厂商： | NXP Semiconductors |
| 文件页数： | 6/80页 |
| 文件大小： | 0K |
| 描述： | IC 80C51 MCU FLASH 16K 44-PLCC |
| 产品培训模块： | Migrating from 8/16-Bit MCUs to 32-Bit ARMs |
| 标准包装： | 156 |
| 系列： | 89V |
| 核心处理器： | 8051 |
| 芯体尺寸： | 8-位 |
| 速度： | 40MHz |
| 连通性： | SPI，UART/USART |
| 外围设备： | 欠压检测/复位，POR，PWM，WDT |
| 输入/输出数： | 32 |
| 程序存储器容量： | 16KB（16K x 8） |
| 程序存储器类型： | 闪存 |
| RAM 容量： | 1K x 8 |
| 电压 - 电源 (Vcc/Vdd)： | 4.5 V ~ 5.5 V |
| 振荡器型： | 内部 |
| 工作温度： | -40°C ~ 85°C |
| 封装/外壳： | 44-LCC（J 形引线） |
| 包装： | 管件 |
| 产品目录页面： | 706 (CN2011-ZH PDF) |
| 配用： | 622-1017-ND - BOARD 44-ZIF PLCC SOCKET 622-1001-ND - USB IN-CIRCUIT PROG 80C51ISP |
| 其它名称： | 568-2427-5 935278706529 P89V51RB2FA-S |
第1页第2页第3页第4页第5页当前第6页第7页第8页第9页第10页第11页第12页第13页第14页第15页第16页第17页第18页第19页第20页第21页第22页第23页第24页第25页第26页第27页第28页第29页第30页第31页第32页第33页第34页第35页第36页第37页第38页第39页第40页第41页第42页第43页第44页第45页第46页第47页第48页第49页第50页第51页第52页第53页第54页第55页第56页第57页第58页第59页第60页第61页第62页第63页第64页第65页第66页第67页第68页第69页第70页第71页第72页第73页第74页第75页第76页第77页第78页第79页第80页
P89V51RB2_RC2_RD2_5
NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 05 — 12 November 2009
14 of 80
NXP Semiconductors
P89V51RB2/RC2/RD2
8-bit microcontrollers with 80C51 core
6.2 Memory organization
The device has separate address spaces for program and data memory.
6.2.1 Flash program memory bank selection
There are two internal ash memory blocks in the device. Block 0 has 16/32/64 kB and is
organized as 128/256/512 sectors, each sector consists of 128 B. Block 1 contains the
IAP/ISP routines and may be enabled such that it overlays the rst 8 kB of the user code
memory. The overlay function is controlled by the combination of the Software Reset Bit
(SWR) at FCF.1 and the Bank Select Bit (BSEL) at FCF.0. The combination of these bits
and the memory source used for instructions is shown in Table 5.
Access to the IAP routines in block 1 may be enabled by clearing the BSEL bit (FCF.0),
provided that the SWR bit (FCF.1) is cleared. Following a power-on sequence, the boot
code is automatically executed and attempts to autobaud to a host. If no autobaud occurs
within approximately 400 ms and the SoftICE ag is not set, control will be passed to the
user code. A software reset is used to accomplish this control transfer and as a result the
SWR bit will remain set. Therefore the user's code will need to clear the SWR bit in
order to access the IAP routines in block 1. However, caution must be taken when
dynamically changing the BSEL bit. Since this will cause different physical memory to be
mapped to the logical program address space, the user must avoid clearing the BSEL bit
when executing user code within the address range 0000H to 1FFFH.
6.2.2 Power-on reset code execution
At initial power up, the port pins will be in a random state until the oscillator has started
and the internal reset algorithm has weakly pulled all pins high. Powering up the device
without a valid reset could cause the MCU to start executing instructions from an
indeterminate location. Such undened states may inadvertently corrupt the code in the
ash. A system reset will not affect the 1 kB of on-chip RAM while the device is running,
however, the contents of the on-chip RAM during power up are indeterminate.
When power is applied to the device, the RST pin must be held high long enough for the
oscillator to start up (usually several milliseconds for a low frequency crystal), in addition
to two machine cycles for a valid power-on reset. An example of a method to extend the
RST signal is to implement a RC circuit by connecting the RST pin to VDD through a 10 F
circuit is being used, provisions should be made to ensure the VDD rise time does not
exceed 1 ms and the oscillator start-up time does not exceed 10 ms.
For a low frequency oscillator with slow start-up time the reset signal must be extended in
order to account for the slow start-up time. This method maintains the necessary
relationship between VDD and RST to avoid programming at an indeterminate location,
which may cause corruption in the code of the ash. The power-on detection is designed
Table 5.
Code memory bank selection
SWR (FCF.1)
BSEL (FCF.0)
Addresses from 0000H to
1FFFH
Addresses above 1FFFH
0
boot code (in block 1)
user code (in block 0)
0
1
user code (in block 0)
10
11
相关PDF资料 |
PDF描述 |
|---|---|
| P89V660FA,512 | IC 80C51 MCU FLASH 16K 44-PLCC |
| P89V660FBC,557 | IC 80C51 MCU FLASH 16K 44-TQFP |
| P89V662FBC,557 | IC 80C51 MCU FLASH 32K 44-TQFP |
| PIC32MX130F064B-I/SO | IC MCU 32BIT 64KB FLASH 28-SOIC |
| PIC32MX220F032D-I/ML | IC MCU 32BIT 32KB FLASH 44QFN |
相关代理商/技术参数 |
参数描述 |
|---|---|
| P89V51RB2FN | 制造商:NXP Semiconductors 功能描述:IC MCU 8BIT 80C51 16K FLASH DIP40 制造商:NXP Semiconductors 功能描述:IC, MCU 8BIT 80C51 16K FLASH, DIP40 |
| P89V51RB2FN,112 | 功能描述:8位微控制器 -MCU 80C51 16K FL / 512 R RoHS:否 制造商:Silicon Labs 核心:8051 处理器系列:C8051F39x 数据总线宽度:8 bit 最大时钟频率:50 MHz 程序存储器大小:16 KB 数据 RAM 大小:1 KB 片上 ADC:Yes 工作电源电压:1.8 V to 3.6 V 工作温度范围:- 40 C to + 105 C 封装 / 箱体:QFN-20 安装风格:SMD/SMT |
| P89V51RB2FN112 | 制造商:NXP Semiconductors 功能描述:IC 8BIT MCU 80C51 40MHZ DIP-40 |
| P89V51RC2 | 制造商:PHILIPS 制造商全称:NXP Semiconductors 功能描述:8-bit 80C51 5 V low power 16/32/64 kB Flash microcontroller with 1 kB RAM |
| P89V51RC2BN | 制造商:PHILIPS 制造商全称:NXP Semiconductors 功能描述:8-bit 80C51 5 V low power 16/32/64 kB Flash microcontroller with 1 kB RAM |
发布紧急采购，3分钟左右您将得到回复。