参数资料
型号: P89V52X2FA,512
厂商: NXP Semiconductors
文件页数: 6/57页
文件大小: 0K
描述: IC 80C51 MCU FLASH 8K 44-PLCC
产品培训模块: Migrating from 8/16-Bit MCUs to 32-Bit ARMs
标准包装: 1,300
系列: 89V
核心处理器: 8051
芯体尺寸: 8-位
速度: 40MHz
连通性: UART/USART
外围设备: POR
输入/输出数: 32
程序存储器容量: 8KB(8K x 8)
程序存储器类型: 闪存
EEPROM 大小: 192 x 8
RAM 容量: 256 x 8
电压 - 电源 (Vcc/Vdd): 2.7 V ~ 5.5 V
振荡器型: 外部
工作温度: -40°C ~ 85°C
封装/外壳: 44-LCC(J 形引线)
包装: 管件
产品目录页面: 706 (CN2011-ZH PDF)
配用: 622-1017-ND - BOARD 44-ZIF PLCC SOCKET
622-1012-ND - BOARD FOR P89V52X2 44-TQFP
622-1008-ND - BOARD FOR LPC9103 10-HVSON
622-1002-ND - USB IN-CIRCUIT PROG LPC9XX
其它名称: 568-4249-5
935282528512
P89V52X2FA
P89V52X2_3
NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 03 — 4 May 2009
14 of 57
NXP Semiconductors
P89V52X2
80C51 with 256 B RAM, 192 B data EEPROM
6.6 Reset
At initial power-up, the port pins will be in a random state until the oscillator has started
and the internal reset algorithm has weakly pulled all pins HIGH. Powering up the device
without a valid reset could cause the device to start executing instructions from an
indeterminate location. Such undened states may inadvertently corrupt the code in the
ash. A system reset will not affect the on-chip RAM while the device is running, however,
the contents of the on-chip RAM during power-up are indeterminate.
When power is applied to the device, the RST pin must be held HIGH long enough for the
oscillator to start-up (usually several milliseconds for a low frequency crystal), in addition
to two machine cycles for a valid power-on reset. An example of a method to extend the
RST signal is to implement a RC circuit by connecting the RST pin to VDD through a 10 F
capacitor and to VSS through an 8.2 k resistor as shown in Figure 9.
During initial power the POF ag in the PCON register is set to indicate an initial power-up
condition. The POF ag will remain active until cleared by software.
Following a reset condition, under normal conditions, the device will start executing code
from address 0000H in the user’s code memory. However if the requirements are met for
ICP entry, the device will enter ICP mode.
Table 9.
AUXR1 - Auxiliary register 1 (address A2H) bit description
Bit
Symbol
Description
7 to 4
-
Reserved for future use. Should be set to ‘0’ by user programs.
3
GF2
General purpose user-dened ag.
2
0
This bit contains a hard-wired ‘0’. Allows toggling of the DPS bit by
incrementing AUXR1, without interfering with other bits in the register.
1
-
Reserved for future use. Should be set to ‘0’ by user programs.
0
DPS
Data pointer select. Chooses one of two Data Pointers for use by the
program. See text for details.
Fig 9.
Power-on reset circuit
002aaa543
VDD
8.2 k
RST
XTAL2
XTAL1
C1
C2
10
F
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